ROM_CTRL/32KB Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.340s	11.222ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.140s	8.242ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.290s	4.279ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.110s	4.023ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.010s	2.780ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.260s	7.605ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.290s	4.279ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.010s	2.780ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.350s	1.776ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.970s	1.527ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.580s	2.134ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.500m	8.040ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.890s	8.509ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.010s	2.147ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.860s	2.051ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.860s	2.051ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.140s	8.242ms	5	5	100.00
		rom_ctrl_csr_rw	17.290s	4.279ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.010s	2.780ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.760s	2.095ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.140s	8.242ms	5	5	100.00
		rom_ctrl_csr_rw	17.290s	4.279ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.010s	2.780ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.760s	2.095ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.342m	39.603ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.778m	7.584ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.318m	10.808ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.778m	7.584ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.778m	7.584ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.778m	7.584ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.340s	11.222ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.340s	11.222ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.340s	11.222ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.318m	10.808ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.890s	8.509ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.279m	50.484ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.342m	39.603ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.778m	7.584ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.862h	66.556ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			465	500	93.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	91.99	97.67	100.00	98.28	97.30	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.5327875416645901228786287173779750995896472574401969923457740348802647915963
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 844142920 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 844142920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.107643058304402508343735218507901712759160071815819890463935973292304846418300
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2274641571 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2274641571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.86492598209280745806660436005843168163034921842078427115052550673123983663276
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:40601b43-cb22-45f1-95c6-f077c0b275be
```
  - 16.rom_ctrl_stress_all_with_rand_reset.99557814065975551522122621094557584180384765956339273902287745897976172372057
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6a5e9f0b-c752-4841-a927-3a6366728001
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.111885959532094036935107005568332098928236477890443330419706297177279017702159
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006417943 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9c976a7f
  UVM_INFO @ 10006417943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.7036494580212857547231222510127753070305624181776987461889323653624314250045
    Line 335, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 130541276114 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x8202df0b
  UVM_INFO @ 130541276114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c42c47ec2d`