ROM_CTRL/32KB Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.540s	3.757ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.640s	3.755ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.060s	1.837ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.740s	10.375ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.030s	5.571ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.490s	2.254ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.060s	1.837ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	5.571ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.710s	1.763ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.050s	1.527ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.990s	2.224ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.249m	12.922ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.810s	4.318ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.170s	8.867ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.920s	1.906ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.920s	1.906ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.640s	3.755ms	5	5	100.00
		rom_ctrl_csr_rw	15.060s	1.837ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	5.571ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.190s	5.918ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.640s	3.755ms	5	5	100.00
		rom_ctrl_csr_rw	15.060s	1.837ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.030s	5.571ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.190s	5.918ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.524m	40.746ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.682m	1.142ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.325m	4.548ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.682m	1.142ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.682m	1.142ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.682m	1.142ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.540s	3.757ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.540s	3.757ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.540s	3.757ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.325m	4.548ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
		rom_ctrl_kmac_err_chk	35.810s	4.318ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.902m	473.106ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.524m	40.746ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.682m	1.142ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.208h	217.300ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	96.89	91.99	97.67	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.41920558886618123128267981213981034944772150406886530366289582037538836203875
    Line 338, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38725603681 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38725603681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.24140270625575780156336017006493782169327890574626076089864959137204162836386
    Line 695, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 217300185079 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 217300185079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.28312974812190094723132582677625228765657219690909105412316318777869419212035
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c70179be-5550-487f-b504-07318e2d8954
```
  - 12.rom_ctrl_stress_all_with_rand_reset.10551695527425593880684131385896993568290121147230326143067937066636537000341
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8371fc9a-4fbd-4736-88db-6ad42e182c3d
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 43.rom_ctrl_stress_all_with_rand_reset.83431410759694671658038277504289782917569318342648002393256128450790602555385
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10014671186 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x367465b5
  UVM_INFO @ 10014671186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.rom_ctrl_stress_all_with_rand_reset.13844075453698314291505918047621633783909491359167943665045072222696604745774
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012708474 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1aeffe8
  UVM_INFO @ 10012708474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 31.rom_ctrl_corrupt_sig_fatal_chk.85905577799750845652780600296417652776661515420313416043237437427471347695161
    Line 292, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 31193001743 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 31193001743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`