ROM_CTRL/32KB Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.020s	8.409ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.700s	9.222ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.460s	8.700ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.300s	4.079ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.200s	3.922ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.820s	2.190ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.460s	8.700ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	3.922ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.690s	10.714ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.350s	3.540ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.440s	25.652ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.187m	33.649ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.100s	8.392ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.610s	4.053ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.280s	4.113ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.280s	4.113ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.700s	9.222ms	5	5	100.00
		rom_ctrl_csr_rw	16.460s	8.700ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	3.922ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.950s	4.340ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.700s	9.222ms	5	5	100.00
		rom_ctrl_csr_rw	16.460s	8.700ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	3.922ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.950s	4.340ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.773m	53.528ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.733m	1.249ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.307m	2.018ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.733m	1.249ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.733m	1.249ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.733m	1.249ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.020s	8.409ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.020s	8.409ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.020s	8.409ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.307m	2.018ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.100s	8.392ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.458m	54.627ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.773m	53.528ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.733m	1.249ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.644h	270.364ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.67	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.103658405069906580673338512030640226368835864160372268710886535030100810694858
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 531782762 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 531782762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.82486167397046623333138363280987726878532724250132339473525072585791922992171
    Line 920, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110406900027 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 110406900027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.49404214927261658176117156339853652485143488982846547825608386192220045539414
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a3d6a9a3-9b37-4976-a735-5e1559141626
```
  - 2.rom_ctrl_stress_all_with_rand_reset.65645579735698645635619132194094608251523070288828991104696242176827918039654
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:adf800c5-f7f4-4623-a2b6-9a1dcfbbad74
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 12.rom_ctrl_stress_all.61617232916025977788180679768226158916102651878488152980711529250409477821342
    Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 80106748626 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xdb83bf2f
  UVM_INFO @ 80106748626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 46.rom_ctrl_stress_all_with_rand_reset.16150762250450694207684277803248248331441071175101945493425512346534984064967
    Line 298, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 52428445651 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc8e07e52
  UVM_INFO @ 52428445651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`