edf2fd5092| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 40.390s | 5.787ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 16.030s | 2.061ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 15.940s | 12.092ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 13.810s | 6.150ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 15.440s | 1.928ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 17.120s | 8.616ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 15.940s | 12.092ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 15.440s | 1.928ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 12.750s | 14.715ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 14.980s | 1.874ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 19.160s | 42.027ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.798m | 55.809ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.190s | 4.065ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.300s | 7.955ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 20.820s | 8.283ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 20.820s | 8.283ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 16.030s | 2.061ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.940s | 12.092ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 15.440s | 1.928ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.830s | 8.060ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 16.030s | 2.061ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.940s | 12.092ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 15.440s | 1.928ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.830s | 8.060ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.728m | 13.115ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.730m | 1.464ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.256m | 3.013ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.730m | 1.464ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.730m | 1.464ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.730m | 1.464ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 40.390s | 5.787ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 40.390s | 5.787ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 40.390s | 5.787ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.256m | 3.013ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 34.190s | 4.065ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 7.157m | 176.460ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.728m | 13.115ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.730m | 1.464ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.761h | 261.313ms | 20 | 50 | 40.00 |
| V3 | TOTAL | 20 | 50 | 40.00 | |||
| TOTAL | 469 | 500 | 93.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.29 | 96.89 | 91.85 | 97.67 | 100.00 | 98.28 | 97.30 | 99.07 |
UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
0.rom_ctrl_stress_all_with_rand_reset.40599314163397285678299885203423644008006106557292946099727132671802466181911
Line 783, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 265476518591 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 265476518591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_ctrl_stress_all_with_rand_reset.46768875683856989197459583855885543071757094834935424540829203274219862269702
Line 323, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9214640868 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9214640868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
11.rom_ctrl_stress_all_with_rand_reset.17783567248469091214758166980166382405162891170464612993231458437509997240969
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:63373da7-ed1a-4a80-929c-744c8cfdc425
27.rom_ctrl_stress_all_with_rand_reset.66560281699115423724685894341559082506604951719117120819823235084233337861738
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d1efa3e8-9b9e-47c7-b818-a67a62c4bdee
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
4.rom_ctrl_stress_all_with_rand_reset.92880960807174586574092478853094346924478924352186349624346004825525506502306
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10024179449 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x460c30be
UVM_INFO @ 10024179449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rom_ctrl_stress_all_with_rand_reset.40792759120130348101538361001206124442593587049762271796524334125731533073936
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10965954768 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x60df6584
UVM_INFO @ 10965954768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
14.rom_ctrl_corrupt_sig_fatal_chk.110268706294586070993205571348786528761799355198863244401530699477515402610567
Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 15811461295 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 15811461295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---