ROM_CTRL/32KB Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.890s	14.019ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.160s	1.554ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.520s	34.202ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.940s	7.434ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.150s	1.849ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.860s	7.903ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.520s	34.202ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.150s	1.849ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.310s	7.167ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.570s	36.786ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.080s	3.252ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.710m	15.950ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.700s	4.382ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.260s	8.579ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.340s	2.078ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.340s	2.078ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.160s	1.554ms	5	5	100.00
		rom_ctrl_csr_rw	17.520s	34.202ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.150s	1.849ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.640s	2.100ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.160s	1.554ms	5	5	100.00
		rom_ctrl_csr_rw	17.520s	34.202ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.150s	1.849ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.640s	2.100ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.605m	14.765ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.822m	10.168ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.335m	7.744ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.822m	10.168ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.822m	10.168ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.822m	10.168ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.890s	14.019ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.890s	14.019ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.890s	14.019ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.335m	7.744ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.700s	4.382ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.689m	97.186ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.605m	14.765ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.822m	10.168ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.599h	295.470ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.67	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.97562965181094968526886938255556718060288290414032200736946819488622037599556
    Line 424, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41007391191 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41007391191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.1983997463469091922240176409411588063331838224288475511384632147312120495594
    Line 541, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35239760463 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35239760463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.39902829443896860723852066950354164657481452849863701584307336954980321627292
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:688c0e7d-0a64-40b5-b99a-c5c0d6394b7b
```
  - 13.rom_ctrl_stress_all_with_rand_reset.86215658272227373808580986410314498154727860374423415941317024577662421425691
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5c0eccbb-3cdb-441a-8da8-60c854174cda
```
  - ... and 12 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.31125633894421453449332299714084520527233603855317394792838562491397232377766
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11217483782 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa7535bd2
  UVM_INFO @ 11217483782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39211701b5`