ROM_CTRL/32KB Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.390s	3.505ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.530s	1.625ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.820s	2.056ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.040s	4.572ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.950s	3.929ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.170s	4.359ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.820s	2.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.950s	3.929ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.160s	3.980ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.700s	4.286ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.130s	2.248ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.631m	16.612ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.900s	4.126ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.860s	19.631ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.390s	2.022ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.390s	2.022ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.530s	1.625ms	5	5	100.00
		rom_ctrl_csr_rw	15.820s	2.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.950s	3.929ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.950s	26.676ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.530s	1.625ms	5	5	100.00
		rom_ctrl_csr_rw	15.820s	2.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.950s	3.929ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.950s	26.676ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.232m	46.474ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.668m	583.557us	5	5	100.00
		rom_ctrl_tl_intg_err	1.324m	2.418ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.668m	583.557us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.668m	583.557us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.668m	583.557us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.390s	3.505ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.390s	3.505ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.390s	3.505ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.324m	2.418ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.900s	4.126ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.898m	49.234ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.232m	46.474ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.668m	583.557us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.392h	93.436ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.89	91.85	97.67	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 33 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.103442187407936650816148558748021561592282838740752248882072472338148044186079
    Line 397, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16450429862 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16450429862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.96804848213826959997169939963549512548138224067503619029269426281161422161075
    Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16326351056 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16326351056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.64698688289760319084340419861368862933738065485923975228364329639592564044494
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:194270a4-2771-4bb3-b855-6a193cd8d8f7
```
  - 11.rom_ctrl_stress_all_with_rand_reset.54275092317123944995710390946566610826919355929446942883211781141230147770962
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a907d99f-6ae4-4880-881f-dc989836a26d
```
  - ... and 3 more failures.

ROM_CTRL/32KB Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5967df933a`