ROM_CTRL/32KB Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.120s	38.446ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.580s	4.339ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.880s	12.303ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.710s	2.577ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.290s	3.974ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.400s	2.113ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.880s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	3.974ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.210s	3.780ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.510s	15.657ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.470s	4.214ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.464m	10.116ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.280s	4.292ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.920s	2.004ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.940s	8.672ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.940s	8.672ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.580s	4.339ms	5	5	100.00
		rom_ctrl_csr_rw	16.880s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	3.974ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.060s	8.461ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.580s	4.339ms	5	5	100.00
		rom_ctrl_csr_rw	16.880s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	3.974ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.060s	8.461ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.458m	42.674ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.851m	19.921ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.306m	1.847ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.851m	19.921ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.851m	19.921ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.851m	19.921ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.120s	38.446ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.120s	38.446ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.120s	38.446ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.306m	1.847ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.280s	4.292ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.792m	109.581ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.458m	42.674ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.851m	19.921ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.326h	75.933ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	96.89	91.99	97.67	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.37980415346737923935894211246963175985566871772753447156653924363130202082372
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 296239729 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 296239729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.45064736869214643179185241771731062670170162829748986353257087974351606381000
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1376734210 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1376734210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 29.rom_ctrl_stress_all_with_rand_reset.15002596903726135087293093443852531007604234567597945752266644278522435353791
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f487d09e-0de5-4892-9fb9-cb69b779bf9f
```
  - 43.rom_ctrl_stress_all_with_rand_reset.53917178003661238812069526052480223608433582788057570668011248486953500719883
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ca77225a-7ad4-467f-b87f-9cc120f6ffb7
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.63461776742279197602431846856147909088523720452228872689623121571916195830738
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11347708881 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc53b35b6
  UVM_INFO @ 11347708881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.rom_ctrl_stress_all_with_rand_reset.31295566944183161557221844887455794713880923638538639928656952311314162468057
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10845760784 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcee65e86
  UVM_INFO @ 10845760784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`