ROM_CTRL/32KB Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.670s	3.624ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.970s	1.598ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.270s	2.007ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.480s	1.744ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.530s	4.381ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.790s	3.476ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.270s	2.007ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.530s	4.381ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.730s	3.591ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.550s	11.674ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.840s	3.219ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.635m	9.609ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.610s	21.235ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.720s	4.196ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.450s	8.184ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.450s	8.184ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.970s	1.598ms	5	5	100.00
		rom_ctrl_csr_rw	15.270s	2.007ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.530s	4.381ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.880s	7.952ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.970s	1.598ms	5	5	100.00
		rom_ctrl_csr_rw	15.270s	2.007ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.530s	4.381ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.880s	7.952ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.392m	22.916ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.764m	1.471ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.315m	4.044ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.764m	1.471ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.764m	1.471ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.764m	1.471ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.670s	3.624ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.670s	3.624ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.670s	3.624ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.315m	4.044ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.610s	21.235ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.456m	150.526ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.392m	22.916ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.764m	1.471ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.974h	163.929ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	96.89	91.85	97.67	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.114451510413691640049706260691359202325475826074459901276732256783836460118600
    Line 378, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 62641635864 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 62641635864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.25150836285650936639120306663115990686219513016089124273823972871237737994049
    Line 695, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175385137578 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 175385137578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.56719386629770969566253423758685020470797320571527403064546140904633644910979
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:884ace99-abb2-4c67-82bf-81289b554f36
```
  - 14.rom_ctrl_stress_all_with_rand_reset.91179951229211303498794179058159197887517248384133637637118475481905310898694
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:77392fe5-5e45-4320-aa57-2d6ed6ae6179
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.40618279075719986422733990934487831261549934078396091541591626151036499770639
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10017548426 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc07702f1
  UVM_INFO @ 10017548426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.rom_ctrl_stress_all_with_rand_reset.108695619143529155546826704860969428373745506855281184660937914186385679644300
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10018000654 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7f69edce
  UVM_INFO @ 10018000654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 39.rom_ctrl_kmac_err_chk.93872163498501604652883095166548562803104593926507276272677941437346366539087
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3317077617 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3317077617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 42.rom_ctrl_stress_all.30963724291141724119748833939162013900377454291328976713005539049319665735325
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40676033213 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x426b4250
  UVM_INFO @ 40676033213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a04e34f557`