ROM_CTRL/32KB Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.960s	3.869ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.520s	1.620ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.910s	2.324ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.500s	6.940ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.020s	8.495ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.840s	2.003ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.910s	2.324ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.020s	8.495ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.380s	2.119ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.670s	5.958ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.410s	4.336ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.891m	46.287ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.540s	16.460ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.510s	8.886ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.130s	2.059ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.130s	2.059ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.520s	1.620ms	5	5	100.00
		rom_ctrl_csr_rw	15.910s	2.324ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.020s	8.495ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.330s	8.841ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.520s	1.620ms	5	5	100.00
		rom_ctrl_csr_rw	15.910s	2.324ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.020s	8.495ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.330s	8.841ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.647m	12.819ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.840m	1.907ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.396m	4.548ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.840m	1.907ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.840m	1.907ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.840m	1.907ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.960s	3.869ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.960s	3.869ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.960s	3.869ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.396m	4.548ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.540s	16.460ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.228m	206.320ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.647m	12.819ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.840m	1.907ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.192h	104.463ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.67	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.23764805598898221327405181512024445152435751771192320428661955673809160687712
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1113072984 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1113072984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.114514131694110019830884084360158607045196029415097372392040454455055210732571
    Line 312, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34995020370 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34995020370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.91927929579625102046265202280180172857066537638411911896491128236862424861871
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:de443d66-b8cc-47d1-9cb0-15a9cad3948a
```
  - 14.rom_ctrl_stress_all_with_rand_reset.9380981759962525254967404696589178951342501382960221258309982632300411086125
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fb6c0c56-8c1e-44eb-9300-060c836a0237
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.83124240955792547517016650359501989085515241535076349207079229549652595851626
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10009486770 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc1bd95f5
  UVM_INFO @ 10009486770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.rom_ctrl_stress_all_with_rand_reset.101388466587363744266490561148944448339015278601026487559044906372170027486909
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11104284519 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xad4f3b0f
  UVM_INFO @ 11104284519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

ROM_CTRL/32KB Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`