ROM_CTRL/32KB Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	18.530s	2.002ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.230s	2.548ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.170s	129.363us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.290s	499.760us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.220s	256.645us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.730s	640.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.170s	129.363us	20	20	100.00
		rom_ctrl_csr_aliasing	5.220s	256.645us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.030s	566.726us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.900s	444.697us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.170s	521.016us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	49.410s	6.488ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.530s	1.967ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.720s	1.533ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.730s	2.081ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.730s	2.081ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.230s	2.548ms	5	5	100.00
		rom_ctrl_csr_rw	5.170s	129.363us	20	20	100.00
		rom_ctrl_csr_aliasing	5.220s	256.645us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.440s	2.230ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.230s	2.548ms	5	5	100.00
		rom_ctrl_csr_rw	5.170s	129.363us	20	20	100.00
		rom_ctrl_csr_aliasing	5.220s	256.645us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.440s	2.230ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	47.220s	6.222ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.744m	333.933us	5	5	100.00
		rom_ctrl_tl_intg_err	1.277m	592.490us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.744m	333.933us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.744m	333.933us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.744m	333.933us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	18.530s	2.002ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	18.530s	2.002ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	18.530s	2.002ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.277m	592.490us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.530s	1.967ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.748m	25.610ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	47.220s	6.222ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.744m	333.933us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.922h	109.765ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			476	500	95.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	96.89	92.13	97.67	100.00	98.62	97.30	98.83

Failure Buckets

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 19 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.81553215499500157914255176398080798094504260216985718869494361898791676563132
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:b7beba49-e83e-449b-a9ff-32ee06b029e0
      

    • 6.rom_ctrl_stress_all_with_rand_reset.13564481872491863191548043553054723962043707950952380835094125460461433890219
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:773ad38f-7c8a-4332-a369-bff6b7dd7b75
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 5.rom_ctrl_stress_all_with_rand_reset.93130601235887896584579261050008330380454423550496003152889161601455654585280
      Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1185863852 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1185863852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.rom_ctrl_stress_all_with_rand_reset.57360185920734251322180968929436616033840722381357069240303991155380559596647
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110040691 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 110040691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

Past Results

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