ROM_CTRL/32KB Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.520s	141.925us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.300s	519.854us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.830s	983.490us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.710s	1.972ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.240s	828.602us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.890s	509.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.830s	983.490us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	828.602us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.110s	536.941us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.100s	128.450us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.910s	6.319ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	27.920s	6.114ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.760s	16.450ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.630s	687.984us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.220s	160.276us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.220s	160.276us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.300s	519.854us	5	5	100.00
		rom_ctrl_csr_rw	7.830s	983.490us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	828.602us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.390s	507.025us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.300s	519.854us	5	5	100.00
		rom_ctrl_csr_rw	7.830s	983.490us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	828.602us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.390s	507.025us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.100s	2.110ms	6	20	30.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.706m	288.841us	5	5	100.00
		rom_ctrl_tl_intg_err	1.296m	639.187us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.706m	288.841us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.706m	288.841us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.706m	288.841us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.520s	141.925us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.520s	141.925us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.520s	141.925us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.296m	639.187us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.760s	16.450ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.795m	3.544ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.100s	2.110ms	6	20	30.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.706m	288.841us	5	5	100.00
V2S		TOTAL			81	95	85.26
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.959h	15.110ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			411	460	89.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.67	100.00	98.62	97.45	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.65609282960021090270927310511886557757854201816586380266346518522694029079832
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5f938ac2-8e5b-4947-90e5-db3583dda3b2
```
  - 6.rom_ctrl_stress_all_with_rand_reset.108461369222305881902778607515440963827276801723878439036420053733580980354629
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d0c9360c-c2de-4e06-bdc1-9c3d98a30bd9
```
  - ... and 15 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed

has 9 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 9 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.108050278128322922505388204320404213068540470763490453120304548026181575388354
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 495283741 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 495283741 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 495283741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.69920070358555789705723075151380402828287297604259383544540567640690519628440
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 495437801 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 495437801 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 495437801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.66596487320423277449835289433506312960772960962253560947277154764202062258632
    Line 396, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15109897657 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 15109897657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.32856089619884763307716983207869270792800672380883350381512552999535031651763
    Line 527, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30192697613 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 30192697613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed

has 5 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 5 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.115701961794720659135275420095191129496983340148506829143701274703953507530955
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 976887522 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 976887522 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 976887522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rom_ctrl_passthru_mem_tl_intg_err.15042894842877558251369091121922467179989344739585099937023240187202851063229
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 519866981 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 519866981 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 519866981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.51876248698631051097750107868367343374689722228240253741205251796293142349114
    Line 286, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5743796781 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5743796781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.rom_ctrl_stress_all_with_rand_reset.87987343475232440872146225551535240802329713258337776564016705650651985826869
    Line 288, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12151746151 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12151746151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.114368602666389565355708946641590033591030479936871999079674856928070526531902
    Line 338, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 32101239622 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 32101239622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rom_ctrl_stress_all_with_rand_reset.42864952319921117194702671237515407575121913600964975963499168763269307837340
    Line 404, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 58999601400 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 58999601400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.3823389140666983748235364522581271778459233219029076660782118654330477596112
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 359924531 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 359924531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rom_ctrl_stress_all_with_rand_reset.16423201925234178026840266106914118316209175246643279736033791764266241148301
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112064474 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 112064474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```