ROM_CTRL/32KB Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.820s	147.857us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.210s	1.613ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.990s	493.881us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.820s	2.066ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.170s	261.688us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.960s	2.170ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.990s	493.881us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	261.688us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.010s	1.554ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.010s	131.641us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.090s	1.006ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	30.080s	1.363ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.140s	3.930ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	7.660s	494.806us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.580s	1.827ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.580s	1.827ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.210s	1.613ms	5	5	100.00
		rom_ctrl_csr_rw	7.990s	493.881us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	261.688us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.010s	145.499us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.210s	1.613ms	5	5	100.00
		rom_ctrl_csr_rw	7.990s	493.881us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	261.688us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.010s	145.499us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.800s	548.066us	8	20	40.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.670m	256.417us	5	5	100.00
		rom_ctrl_tl_intg_err	1.181m	591.104us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.670m	256.417us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.670m	256.417us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.670m	256.417us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.820s	147.857us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.820s	147.857us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.820s	147.857us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.181m	591.104us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.140s	3.930ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.567m	17.704ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.800s	548.066us	8	20	40.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.670m	256.417us	5	5	100.00
V2S		TOTAL			83	95	87.37
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.575h	47.278ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			413	460	89.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.67	100.00	98.62	97.30	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.100136881797938856469119605983523552467548429328206992740398728797528077591302
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0c540c56-1f7a-4878-a26f-a0bf8e6467f5
```
  - 1.rom_ctrl_stress_all_with_rand_reset.54485754273151415137619829082515487257103981739631348646958520145215713859444
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:73bf13a4-1b4d-415a-9380-f6c6b8eccae8
```
  - ... and 13 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 9 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 9 failures.

3.rom_ctrl_passthru_mem_tl_intg_err.30922321045962535549480783493294957677931223058215778701398673104347934808288
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @  84159562 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @  84159562 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @  84159562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.rom_ctrl_passthru_mem_tl_intg_err.54458665856349030729372010480010127752204986827513293280114456471113799872928
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1096307849 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 1096307849 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1096307849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.22866831567212546673625822480956856071688587774287282085330886894669851470559
    Line 316, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5939547668 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5939547668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rom_ctrl_stress_all_with_rand_reset.11225361397197604981003008325179719564737892005285643100263941804674773591217
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181152715 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 181152715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.27635958819942041731752589397557166328174242249986483015362310739127974103151
    Line 493, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 47278133294 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 47278133294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.90144210628177957631175078040582180109691350333154424348995046287557335564447
    Line 420, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 264067344179 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 264067344179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 28.rom_ctrl_stress_all_with_rand_reset.64547001040517190604241541049561513071093273773529567648106069770086601112014
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 988962168 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 988962168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rom_ctrl_stress_all_with_rand_reset.51414090352545150053214439439214386089404965128710510803814338468069046557482
    Line 880, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46009680581 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 46009680581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

5.rom_ctrl_passthru_mem_tl_intg_err.43468672279763350677344211238262396715449055442185531750519230264516074342760
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2858545118 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 2858545118 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2858545118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.rom_ctrl_passthru_mem_tl_intg_err.56827122727911551791383686139909459062967478659779606844301411247265806341704
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 256688259 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 256688259 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 256688259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 24.rom_ctrl_stress_all_with_rand_reset.42555239474799029778620497597022888615654985999817119180490300583472291496896
    Line 310, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4412360166 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4412360166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.rom_ctrl_stress_all_with_rand_reset.47000374570277318048939838174694457050367511512497791981262628496594670375176
    Line 278, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13975717306 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 13975717306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 1.rom_ctrl_kmac_err_chk.105798194663285137687027216787972807414964905844873779159185156276970744123539
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3309714052 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3309714052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```