ROM_CTRL/32KB Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.740s	142.481us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.570s	512.988us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.370s	1.988ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.330s	129.723us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.160s	130.564us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.040s	1.056ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.370s	1.988ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.160s	130.564us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.940s	879.029us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.830s	127.290us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.750s	1.981ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	27.690s	1.571ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	15.450s	990.348us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.460s	492.479us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.560s	182.099us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.560s	182.099us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.570s	512.988us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	1.988ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.160s	130.564us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.600s	4.134ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.570s	512.988us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	1.988ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.160s	130.564us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.600s	4.134ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.440s	2.362ms	6	20	30.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.691m	327.543us	5	5	100.00
		rom_ctrl_tl_intg_err	1.189m	345.953us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.691m	327.543us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.691m	327.543us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.691m	327.543us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.740s	142.481us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.740s	142.481us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.740s	142.481us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.189m	345.953us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
		rom_ctrl_kmac_err_chk	15.450s	990.348us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.318m	7.953ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.440s	2.362ms	6	20	30.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.691m	327.543us	5	5	100.00
V2S		TOTAL			81	95	85.26
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.787h	23.705ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			414	460	90.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.67	100.00	98.28	97.45	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.15506022712230354250141576617205525517669173602077439407205623059736708074376
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1222d1bc-ccd5-42e0-afa7-bf13f1d943e1
```
  - 3.rom_ctrl_stress_all_with_rand_reset.34746842269262077965023790231692648272788343195505369361017035854345818915656
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:15028f09-0472-4d8b-83de-123f6a676a2e
```
  - ... and 7 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 8 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 8 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.73643553830469166618789040420177033928251459903288164816898558150326459861816
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1059928590 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 1059928590 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1059928590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rom_ctrl_passthru_mem_tl_intg_err.17645932164638003946313795165761137095774696326303495157200108133292152181893
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 266044395 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_4' while it is being accessed
  UVM_ERROR @ 266044395 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 266044395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.66667951947919230125943467430718565243584153105474239553914586847912592455731
    Line 801, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57670736064 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 57670736064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.97199224524460219166887851274607575882254200986384478298276133016241826101110
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 572747975 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 572747975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.43110214694836847871069060203227546474358039549257855941248871894489841548011
    Line 364, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15395415126 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15395415126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.112718644895613467220556941239687602291866778106573462809600767401600790785656
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3077012170 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3077012170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 6 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 6 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.110620658983163686124438615804096460056303038100632926023706618132858751651155
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 634914696 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 634914696 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 634914696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.83697499770670298173998206183599741755945127692465126684245208785801650152062
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 129466117 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 129466117 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 129466117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.98940469792461492130238474522117311880488857576315883070470126786186642399775
    Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 220795094 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 220795094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.14766406359864279745169569525399227908045957790888536020793850084862345942483
    Line 343, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 40690394903 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 40690394903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 46.rom_ctrl_stress_all.112834556595560189931018712247317223296345182344899396834515803404285983546429
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 5680735934 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5680735934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.rom_ctrl_stress_all_with_rand_reset.50802853712623615982293215615166703917217666024147131071265969959212402940835
    Line 1269, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1899901151044 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1899901151044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.rom_ctrl_stress_all_with_rand_reset.80501709258564014589065192161510379149253839341576592103985759303516731417719
    Line 366, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11296860858 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 11296860858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```