ROM_CTRL/32KB Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.390s	524.487us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.510s	133.165us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.280s	880.970us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.960s	2.037ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.030s	500.239us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.940s	282.715us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.280s	880.970us	20	20	100.00
		rom_ctrl_csr_aliasing	5.030s	500.239us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.130s	250.090us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.140s	542.314us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.890s	528.881us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	26.310s	2.162ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.550s	1.178ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.870s	509.711us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.160s	494.101us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.160s	494.101us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.510s	133.165us	5	5	100.00
		rom_ctrl_csr_rw	7.280s	880.970us	20	20	100.00
		rom_ctrl_csr_aliasing	5.030s	500.239us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.860s	7.002ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.510s	133.165us	5	5	100.00
		rom_ctrl_csr_rw	7.280s	880.970us	20	20	100.00
		rom_ctrl_csr_aliasing	5.030s	500.239us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.860s	7.002ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	28.350s	550.101us	6	20	30.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.727m	345.854us	5	5	100.00
		rom_ctrl_tl_intg_err	1.328m	2.237ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.727m	345.854us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.727m	345.854us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.727m	345.854us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.390s	524.487us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.390s	524.487us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.390s	524.487us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.328m	2.237ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
		rom_ctrl_kmac_err_chk	16.550s	1.178ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.640m	76.898ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	28.350s	550.101us	6	20	30.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.727m	345.854us	5	5	100.00
V2S		TOTAL			79	95	83.16
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.601h	44.087ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			411	460	89.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.67	100.00	98.62	97.45	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.538480997506405899480602588160772980116736961649279427730266825635844294930
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:31eac340-58e5-40ac-bd51-4b4c93ff69b6
```
  - 3.rom_ctrl_stress_all_with_rand_reset.66225170223369783706343677038213236171638467841759868854020371123519772766362
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ac3e8b66-540f-489d-afa0-5c2a4d4f2204
```
  - ... and 17 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 13 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 13 failures.

2.rom_ctrl_passthru_mem_tl_intg_err.75073974723944751672185562730342619252476812761925713522628807497337740844533
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 179825835 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 179825835 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 179825835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.101512113366988124246348487532185283216103166870799089165092061447678934732399
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 261635581 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 261635581 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 261635581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.69681644619910098219938611105091171377951815979148469541350712100573430578744
    Line 376, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42352592619 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42352592619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.12435939850253879267239714072955914785853286533919179042615676554945818515165
    Line 392, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34134832858 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34134832858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.2634456896974779833726014568287231981096734589507359447301249214066813488173
    Line 275, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3266929652 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3266929652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.36411719911481568426931197050482395115068946969476261394158255578492393036
    Line 265, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1277279469 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1277279469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 16.rom_ctrl_corrupt_sig_fatal_chk.80271263023229574417048601302200585290260150173975633133646730870554035841519
    Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 17620300847 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 17620300847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.rom_ctrl_corrupt_sig_fatal_chk.64866646649909997400666141958354142630571147447128922140650412519406902521803
    Line 302, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 68231412745 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 68231412745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.29166868965983270689433536311262540607312490048143807019186768687317338402541
    Line 417, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16655189365 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16655189365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.rom_ctrl_stress_all_with_rand_reset.27339068955744289515077443215261519822801830798966355214493314321465596207966
    Line 346, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16442634737 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16442634737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 5.rom_ctrl_passthru_mem_tl_intg_err.72384318796667519872248562398837675430884749696843333636493399313273831460271
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_WARNING @ 378478405 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 378478405 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 378478405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```