ROM_CTRL/32KB Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.190s	3.139ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.780s	500.378us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.140s	153.045us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.310s	133.946us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.460s	1.914ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.810s	581.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.140s	153.045us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.914ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.020s	129.774us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.110s	520.911us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.860s	524.283us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	26.240s	8.861ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.420s	986.876us	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	7.760s	2.577ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.250s	784.653us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.250s	784.653us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.780s	500.378us	5	5	100.00
		rom_ctrl_csr_rw	5.140s	153.045us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.914ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.070s	143.764us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.780s	500.378us	5	5	100.00
		rom_ctrl_csr_rw	5.140s	153.045us	20	20	100.00
		rom_ctrl_csr_aliasing	7.460s	1.914ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.070s	143.764us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.250s	540.908us	4	20	20.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.780m	495.135us	5	5	100.00
		rom_ctrl_tl_intg_err	1.208m	1.320ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.780m	495.135us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.780m	495.135us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.780m	495.135us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.190s	3.139ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.190s	3.139ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.190s	3.139ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.208m	1.320ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.420s	986.876us	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.177m	5.533ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.250s	540.908us	4	20	20.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.780m	495.135us	5	5	100.00
V2S		TOTAL			79	95	83.16
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.584h	29.340ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			415	460	90.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	96.89	91.99	97.67	100.00	98.62	97.30	98.37

Failure Buckets

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 15 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 15 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.6560478177652667775688183338987477693162114496106998153670851902263701446653
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 276569780 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 276569780 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 276569780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_ctrl_passthru_mem_tl_intg_err.64949267142760346665700422583405538022761782380013084555502056433351745920255
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 345000182 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 345000182 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 345000182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.68622530767879767440329611183986562189077697723780558725190345746257256655599
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8d54d3c2-b172-4b8c-85f9-85ba90c94a3b
```
  - 12.rom_ctrl_stress_all_with_rand_reset.2174273163348482393073538015748617631123285201447946803508311357204713510960
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ff636da3-1b4e-49bf-bd4d-a0262896fb3d
```
  - ... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.53654449122843707014241723307246831344524012205305995904720668991243940920312
    Line 280, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2901949446 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2901949446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.rom_ctrl_stress_all_with_rand_reset.58062217592141554683124724907228781302863651901492467819607914479623057329126
    Line 356, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61366578900 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 61366578900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.45122914293830064098320320403667654424358731333977575527211401786419397562035
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 319291821 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 319291821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.79876378863200755431248142347897054919188276947757872730201854742636944575653
    Line 340, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8050436607 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8050436607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.57287995063136223121336561157390904765014491934133910434914456457031337841534
    Line 880, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 275843368931 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 275843368931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.rom_ctrl_stress_all_with_rand_reset.77136047047963583576565857397902919997309181488031560646738614890541288887962
    Line 418, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16115448822 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16115448822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.rom_ctrl_stress_all_with_rand_reset.30510394709091165008221297662525412896182905847400909801472151069811504638157
    Line 1375, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1647983008296 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1647983008296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 48.rom_ctrl_kmac_err_chk.88180103747333208523541530891734932346611694081541635983513870714614734547263
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3315261151 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3315261151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 17.rom_ctrl_passthru_mem_tl_intg_err.112335006438686975757728734067723594320447065525901334424011435752353868029350
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_WARNING @ 510520644 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 510520644 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 510520644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```