ROM_CTRL/32KB Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.440s 529.703us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.300s 405.575us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 6.910s 514.161us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.050s 132.046us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.970s 130.559us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.890s 9.870ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.910s 514.161us 20 20 100.00
rom_ctrl_csr_aliasing 4.970s 130.559us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 4.200s 363.766us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.750s 127.279us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.310s 525.586us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 25.680s 1.129ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.640s 3.172ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 6.700s 515.527us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.910s 524.878us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.910s 524.878us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.300s 405.575us 5 5 100.00
rom_ctrl_csr_rw 6.910s 514.161us 20 20 100.00
rom_ctrl_csr_aliasing 4.970s 130.559us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.640s 135.270us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.300s 405.575us 5 5 100.00
rom_ctrl_csr_rw 6.910s 514.161us 20 20 100.00
rom_ctrl_csr_aliasing 4.970s 130.559us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.640s 135.270us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 41.600s 11.979ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.671m 323.976us 5 5 100.00
rom_ctrl_tl_intg_err 1.157m 621.792us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.671m 323.976us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.671m 323.976us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.671m 323.976us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.440s 529.703us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.440s 529.703us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.440s 529.703us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.157m 621.792us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
rom_ctrl_kmac_err_chk 14.640s 3.172ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.732m 51.743ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 41.600s 11.979ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.671m 323.976us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.258m 5.498ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 454 460 98.70

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.39 96.89 91.99 97.67 100.00 98.28 98.05 98.83

Failure Buckets

Past Results