ROM_CTRL/32KB Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.340s	508.106us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.730s	503.513us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.740s	1.654ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.000s	2.439ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.810s	502.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.290s	2.088ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.740s	1.654ms	20	20	100.00
		rom_ctrl_csr_aliasing	4.810s	502.011us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.760s	505.172us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.850s	132.908us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.080s	2.082ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	31.150s	8.052ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.050s	1.030ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.030s	518.407us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.100s	170.013us	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.100s	170.013us	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.730s	503.513us	5	5	100.00
		rom_ctrl_csr_rw	6.740s	1.654ms	20	20	100.00
		rom_ctrl_csr_aliasing	4.810s	502.011us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.610s	549.917us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.730s	503.513us	5	5	100.00
		rom_ctrl_csr_rw	6.740s	1.654ms	20	20	100.00
		rom_ctrl_csr_aliasing	4.810s	502.011us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.610s	549.917us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.320s	1.706ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.693m	377.866us	5	5	100.00
		rom_ctrl_tl_intg_err	1.234m	2.198ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.693m	377.866us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.693m	377.866us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.693m	377.866us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.340s	508.106us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.340s	508.106us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.340s	508.106us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.234m	2.198ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
		rom_ctrl_kmac_err_chk	14.050s	1.030ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.750m	52.307ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.320s	1.706ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.693m	377.866us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.338m	82.239ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			454	460	98.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	96.89	92.56	97.67	100.00	98.62	97.90	99.77

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.52691147985887439223057942076616320027597561913493611188568699733477631278078
    Line 355, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11674538582 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 11674538582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.72650915749275011742302432402670720316318020031245975025246912952921869501741
    Line 292, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 613515120 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 613515120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 8.rom_ctrl_tl_errors.50405196159975249873670150807248114259825650171925172732516429269804232149909
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1383759679 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1383759679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e45ccd274a`