ROM_CTRL/32KB Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.160s 276.769us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.630s 96.724us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.240s 731.582us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.250s 334.455us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.200s 126.813us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.970s 8.370ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.240s 731.582us 20 20 100.00
rom_ctrl_csr_aliasing 7.200s 126.813us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 6.730s 132.285us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.560s 127.210us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 12.480s 997.297us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 31.830s 544.180us 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.250s 3.984ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 9.610s 497.990us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.620s 170.528us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.620s 170.528us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.630s 96.724us 5 5 100.00
rom_ctrl_csr_rw 7.240s 731.582us 20 20 100.00
rom_ctrl_csr_aliasing 7.200s 126.813us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.560s 589.623us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.630s 96.724us 5 5 100.00
rom_ctrl_csr_rw 7.240s 731.582us 20 20 100.00
rom_ctrl_csr_aliasing 7.200s 126.813us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.560s 589.623us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.390s 1.611ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.938m 264.196us 5 5 100.00
rom_ctrl_tl_intg_err 1.458m 784.700us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.938m 264.196us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.938m 264.196us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.938m 264.196us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.160s 276.769us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.160s 276.769us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.160s 276.769us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.458m 784.700us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
rom_ctrl_kmac_err_chk 17.250s 3.984ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 4.874m 14.417ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.390s 1.611ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.938m 264.196us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 7.110m 23.865ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 457 460 99.35

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.53 96.89 92.56 97.67 100.00 98.62 97.90 99.06

Failure Buckets

Past Results