ROM_CTRL/32KB Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 13.770s 2.107ms 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.880s 238.791us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 8.930s 165.378us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.290s 607.818us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.000s 534.795us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.850s 183.786us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.930s 165.378us 20 20 100.00
rom_ctrl_csr_aliasing 8.000s 534.795us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 7.360s 125.543us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.170s 294.242us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 12.260s 589.073us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 27.240s 585.072us 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 22.890s 1.926ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 11.210s 1.024ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.980s 197.201us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.980s 197.201us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.880s 238.791us 5 5 100.00
rom_ctrl_csr_rw 8.930s 165.378us 20 20 100.00
rom_ctrl_csr_aliasing 8.000s 534.795us 5 5 100.00
rom_ctrl_same_csr_outstanding 10.860s 508.476us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.880s 238.791us 5 5 100.00
rom_ctrl_csr_rw 8.930s 165.378us 20 20 100.00
rom_ctrl_csr_aliasing 8.000s 534.795us 5 5 100.00
rom_ctrl_same_csr_outstanding 10.860s 508.476us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 51.380s 3.437ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.010m 1.384ms 5 5 100.00
rom_ctrl_tl_intg_err 1.549m 478.041us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.010m 1.384ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.010m 1.384ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.010m 1.384ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 13.770s 2.107ms 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 13.770s 2.107ms 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 13.770s 2.107ms 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.549m 478.041us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
rom_ctrl_kmac_err_chk 22.890s 1.926ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 4.368m 4.504ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 51.380s 3.437ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.010m 1.384ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.440m 28.097ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 457 460 99.35

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.87 99.36 92.56 97.67 100.00 98.55 97.91 99.06

Failure Buckets

Past Results