ROM_CTRL/32KB Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.450s	1.966ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.280s	461.998us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.960s	169.942us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.160s	5.490ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.350s	214.149us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.680s	284.646us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.960s	169.942us	20	20	100.00
		rom_ctrl_csr_aliasing	8.350s	214.149us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.690s	171.223us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.700s	299.647us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.560s	2.110ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	31.140s	415.076us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	20.090s	1.571ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	11.170s	2.096ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.040s	1.939ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.040s	1.939ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.280s	461.998us	5	5	100.00
		rom_ctrl_csr_rw	7.960s	169.942us	20	20	100.00
		rom_ctrl_csr_aliasing	8.350s	214.149us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.630s	577.604us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.280s	461.998us	5	5	100.00
		rom_ctrl_csr_rw	7.960s	169.942us	20	20	100.00
		rom_ctrl_csr_aliasing	8.350s	214.149us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.630s	577.604us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	50.140s	6.293ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.328m	383.090us	5	5	100.00
		rom_ctrl_tl_intg_err	1.502m	687.759us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.328m	383.090us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.328m	383.090us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.328m	383.090us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.450s	1.966ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.450s	1.966ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.450s	1.966ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.502m	687.759us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
		rom_ctrl_kmac_err_chk	20.090s	1.571ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.445m	5.446ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	50.140s	6.293ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.328m	383.090us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.263m	4.862ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			452	460	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.36	92.13	97.67	100.00	98.55	98.06	99.06

Failure Buckets

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 8 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 8 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.44882411959846748960873460258836938913686097444363283835639010561576286805775
      Line 138, in log /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 5896064549 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 5896064549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.rom_ctrl_stress_all_with_rand_reset.50431769917492762756950115197289758172537299892146120772064085169324377853957
      Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 4493999567 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 4493999567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

Past Results

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