ROM_CTRL/32KB Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.350s 276.441us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.130s 134.392us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 8.140s 509.856us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.050s 659.409us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.760s 368.535us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.880s 506.260us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.140s 509.856us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 368.535us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 4.530s 129.325us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.930s 132.442us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 11.860s 1.673ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 30.070s 4.252ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.700s 986.225us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 9.720s 513.516us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.690s 257.033us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.690s 257.033us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.130s 134.392us 5 5 100.00
rom_ctrl_csr_rw 8.140s 509.856us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 368.535us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.020s 516.183us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.130s 134.392us 5 5 100.00
rom_ctrl_csr_rw 8.140s 509.856us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 368.535us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.020s 516.183us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 48.070s 6.092ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.026m 1.199ms 5 5 100.00
rom_ctrl_tl_intg_err 1.363m 272.350us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.026m 1.199ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.026m 1.199ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.026m 1.199ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.350s 276.441us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.350s 276.441us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.350s 276.441us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.363m 272.350us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
rom_ctrl_kmac_err_chk 16.700s 986.225us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.776m 55.362ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 48.070s 6.092ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.026m 1.199ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.724m 55.272ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 458 460 99.57

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.41 96.77 92.13 97.67 100.00 98.19 98.06 99.06

Failure Buckets

Past Results