ROM_CTRL/32KB Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.730s 137.136us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.810s 924.746us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.530s 133.655us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.690s 694.694us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 10.220s 498.152us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.030s 139.613us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.530s 133.655us 20 20 100.00
rom_ctrl_csr_aliasing 10.220s 498.152us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 9.860s 493.336us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.410s 273.018us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 12.840s 535.898us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 30.350s 1.350ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 23.360s 1.662ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 11.050s 556.969us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.060s 88.867us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.060s 88.867us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.810s 924.746us 5 5 100.00
rom_ctrl_csr_rw 7.530s 133.655us 20 20 100.00
rom_ctrl_csr_aliasing 10.220s 498.152us 5 5 100.00
rom_ctrl_same_csr_outstanding 11.690s 1.000ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.810s 924.746us 5 5 100.00
rom_ctrl_csr_rw 7.530s 133.655us 20 20 100.00
rom_ctrl_csr_aliasing 10.220s 498.152us 5 5 100.00
rom_ctrl_same_csr_outstanding 11.690s 1.000ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 47.260s 6.243ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.515m 376.673us 5 5 100.00
rom_ctrl_tl_intg_err 1.654m 295.209us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.515m 376.673us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.515m 376.673us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.515m 376.673us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.730s 137.136us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.730s 137.136us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.730s 137.136us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.654m 295.209us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
rom_ctrl_kmac_err_chk 23.360s 1.662ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.794m 8.050ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 47.260s 6.243ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.515m 376.673us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.560m 4.231ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 457 460 99.35

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.49 96.77 91.99 97.67 100.00 98.19 98.06 99.77

Failure Buckets

Past Results