ROM_CTRL/32KB Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.710s	524.666us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.500s	368.677us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.300s	1.971ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.040s	134.506us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.670s	732.999us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.610s	10.180ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.300s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.670s	732.999us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.650s	256.058us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.210s	1.032ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.230s	1.050ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	39.310s	806.728us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	18.870s	3.799ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	11.590s	504.287us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.370s	585.861us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.370s	585.861us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.500s	368.677us	5	5	100.00
		rom_ctrl_csr_rw	10.300s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.670s	732.999us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.630s	225.678us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.500s	368.677us	5	5	100.00
		rom_ctrl_csr_rw	10.300s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.670s	732.999us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.630s	225.678us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	41.510s	3.134ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.240m	329.934us	5	5	100.00
		rom_ctrl_tl_intg_err	1.541m	446.953us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.240m	329.934us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.240m	329.934us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.240m	329.934us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.710s	524.666us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.710s	524.666us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.710s	524.666us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.541m	446.953us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
		rom_ctrl_kmac_err_chk	18.870s	3.799ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.149m	75.804ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	41.510s	3.134ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.240m	329.934us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.725m	21.826ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			457	460	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.36	96.77	92.13	97.67	100.00	98.19	97.91	98.83

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.rom_ctrl_stress_all_with_rand_reset.32543403000638972048023206262257087499208010395182581940390654789103377130529
    Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 202465069 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 202465069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.rom_ctrl_stress_all_with_rand_reset.19154714528318076789162253822973108048258358269406402149413973892854196533012
    Line 100, in log /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1716334557 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1716334557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.60678914977619701718891941667463865362143578587831265834873630035684127990418
    Line 188, in log /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 62058626059 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 62058626059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `78ad89d1aa`