ROM_CTRL/32KB Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.170s 140.522us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.600s 132.582us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.230s 127.398us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.190s 134.159us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.840s 127.612us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 10.610s 509.486us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.230s 127.398us 20 20 100.00
rom_ctrl_csr_aliasing 5.840s 127.612us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 5.900s 311.596us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.130s 499.606us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 10.000s 274.140us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 37.700s 1.152ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 23.980s 2.025ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 10.060s 529.050us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.470s 630.787us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.470s 630.787us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.600s 132.582us 5 5 100.00
rom_ctrl_csr_rw 7.230s 127.398us 20 20 100.00
rom_ctrl_csr_aliasing 5.840s 127.612us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.610s 92.455us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.600s 132.582us 5 5 100.00
rom_ctrl_csr_rw 7.230s 127.398us 20 20 100.00
rom_ctrl_csr_aliasing 5.840s 127.612us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.610s 92.455us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.750s 1.269ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.339m 909.991us 5 5 100.00
rom_ctrl_tl_intg_err 1.397m 760.703us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.339m 909.991us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.339m 909.991us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.339m 909.991us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.170s 140.522us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.170s 140.522us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.170s 140.522us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.397m 760.703us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
rom_ctrl_kmac_err_chk 23.980s 2.025ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.779m 63.684ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.750s 1.269ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.339m 909.991us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.298m 21.188ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 460 460 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.42 96.89 92.13 97.67 100.00 98.28 97.90 99.06

Past Results