ROM_CTRL/64KB Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.565m	34.486ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.380s	17.159ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	28.420s	7.151ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.940s	15.403ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	30.950s	15.786ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.870s	17.190ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	28.420s	7.151ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.950s	15.786ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.180s	35.805ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	29.680s	14.422ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.750s	17.261ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.808m	23.034ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.151m	17.711ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.500s	17.611ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	35.070s	8.447ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	35.070s	8.447ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.380s	17.159ms	5	5	100.00
		rom_ctrl_csr_rw	28.420s	7.151ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.950s	15.786ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.300s	7.209ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.380s	17.159ms	5	5	100.00
		rom_ctrl_csr_rw	28.420s	7.151ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.950s	15.786ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.300s	7.209ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.361m	104.593ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.119m	14.737ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.921m	8.080ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.119m	14.737ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.119m	14.737ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.119m	14.737ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.565m	34.486ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.565m	34.486ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.565m	34.486ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.921m	8.080ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.151m	17.711ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.541m	714.124ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.361m	104.593ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.119m	14.737ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.812h	54.133ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.50	96.97	92.87	97.88	100.00	98.37	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.26125626366926396408522223091253922938785031486332782695871987178733357486370
    Line 429, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32750234277 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32750234277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.32624851573282608214477874600205898330325716588093638178050435763242428776803
    Line 1076, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 539250396507 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 539250396507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.74124170072759306302336018179250678409835385285143342937561893528561773563414
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11079842285 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x164ca174
  UVM_INFO @ 11079842285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.99566368820069706642697026638550731769238555166346812114577895944750445175094
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004946989 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x62b4f485
  UVM_INFO @ 10004946989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.2492107687047679733341097255592182116687403298229846839813426107890532078340
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:dc003987-6f6d-43a6-964b-531cc85ab483
```
  - 8.rom_ctrl_stress_all_with_rand_reset.86619383455451981213950354478725718784335356812665182255370629523971123133793
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:26f0f881-0beb-4772-a1b2-80e896ab16c1
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 32.rom_ctrl_stress_all.86414119694982131393509688137085239449942082033061604723652492954735280827013
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40023640082 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x20d7642a
  UVM_INFO @ 40023640082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.rom_ctrl_stress_all_with_rand_reset.103296918932244017343786481749578593961717547041764632282011478986124801412078
    Line 487, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 248317470702 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 248317470702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `18c8953cf1`