9656691e03
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 1.376m | 16.095ms | 49 | 50 | 98.00 |
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 36.520s | 3.542ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 30.490s | 13.193ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 30.630s | 3.690ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 28.250s | 13.675ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 34.850s | 4.436ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 30.490s | 13.193ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 28.250s | 13.675ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 22.150s | 9.165ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 19.920s | 1.928ms | 5 | 5 | 100.00 |
V1 | TOTAL | 114 | 115 | 99.13 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.800s | 17.398ms | 50 | 50 | 100.00 |
V2 | stress_all | rom_ctrl_stress_all | 3.099m | 80.342ms | 48 | 50 | 96.00 |
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.124m | 17.074ms | 50 | 50 | 100.00 |
V2 | alert_test | rom_ctrl_alert_test | 33.820s | 8.426ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 35.470s | 38.197ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 35.470s | 38.197ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 36.520s | 3.542ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 30.490s | 13.193ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 28.250s | 13.675ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 35.390s | 16.278ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 36.520s | 3.542ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 30.490s | 13.193ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 28.250s | 13.675ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 35.390s | 16.278ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 238 | 240 | 99.17 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 2.975m | 43.237ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 4.162m | 16.914ms | 5 | 5 | 100.00 |
rom_ctrl_tl_intg_err | 2.906m | 8.182ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.162m | 16.914ms | 5 | 5 | 100.00 |
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.162m | 16.914ms | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.162m | 16.914ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.376m | 16.095ms | 49 | 50 | 98.00 |
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.376m | 16.095ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.376m | 16.095ms | 49 | 50 | 98.00 |
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.906m | 8.182ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
rom_ctrl_kmac_err_chk | 1.124m | 17.074ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 15.812m | 91.598ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 2.975m | 43.237ms | 20 | 20 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.162m | 16.914ms | 5 | 5 | 100.00 |
V2S | TOTAL | 95 | 95 | 100.00 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.011h | 84.065ms | 8 | 50 | 16.00 |
V3 | TOTAL | 8 | 50 | 16.00 | |||
TOTAL | 455 | 500 | 91.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 6 | 6 | 5 | 83.33 |
V2S | 4 | 4 | 4 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.54 | 96.97 | 93.01 | 97.88 | 100.00 | 98.69 | 97.88 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 32 failures:
0.rom_ctrl_stress_all_with_rand_reset.10265178299802790536835485373663006569016835972162126453574113685966906220502
Line 681, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 483268611730 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 483268611730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.15217569182985704736965784411777298441165107729698509248074573672590317744861
Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5075363550 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5075363550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=*
has 6 failures:
2.rom_ctrl_stress_all_with_rand_reset.114814726885346057913264030106382084457654608895741592239233930512600195473401
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10004293240 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa807e031
UVM_INFO @ 10004293240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rom_ctrl_stress_all_with_rand_reset.28366352911467974991862746561539532899092127944110908904590961748234172861134
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10709535991 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x98dd7a9c
UVM_INFO @ 10709535991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 3 failures:
9.rom_ctrl_stress_all_with_rand_reset.36175846761038274416834777622268403680357373448493162030823210796935169515593
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8bf1f083-5e0a-49b3-83b2-cdea54045047
19.rom_ctrl_stress_all_with_rand_reset.115273182616404018657138443704553126316946399879783351292289693120867541325327
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:6a931330-2a43-4b06-968f-443ab999d486
... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=*
has 3 failures:
Test rom_ctrl_smoke has 1 failures.
14.rom_ctrl_smoke.13172650993566424698561390684187439457317266774649045722450942359187245646036
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 79911957393 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa6eb14bb
UVM_INFO @ 79911957393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all has 2 failures.
26.rom_ctrl_stress_all.63076280184851988728975077454432919748957035159791985153599480601891149303014
Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40086399893 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x62f47b3b
UVM_INFO @ 40086399893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.rom_ctrl_stress_all.37955997874869227190923113248039331723307607862500591606225028820173002508170
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40017696216 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4e9c0e3a
UVM_INFO @ 40017696216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked
has 1 failures:
44.rom_ctrl_stress_all_with_rand_reset.14546819248996921888980462801914798998846749657961319268325708891599346488460
Line 821, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 644019894470 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 644019894470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---