ROM_CTRL/64KB Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 1.376m 16.095ms 49 50 98.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 36.520s 3.542ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 30.490s 13.193ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 30.630s 3.690ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 28.250s 13.675ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 34.850s 4.436ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 30.490s 13.193ms 20 20 100.00
rom_ctrl_csr_aliasing 28.250s 13.675ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 22.150s 9.165ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 19.920s 1.928ms 5 5 100.00
V1 TOTAL 114 115 99.13
V2 max_throughput_chk rom_ctrl_max_throughput_chk 35.800s 17.398ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 3.099m 80.342ms 48 50 96.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 1.124m 17.074ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 33.820s 8.426ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 35.470s 38.197ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 35.470s 38.197ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 36.520s 3.542ms 5 5 100.00
rom_ctrl_csr_rw 30.490s 13.193ms 20 20 100.00
rom_ctrl_csr_aliasing 28.250s 13.675ms 5 5 100.00
rom_ctrl_same_csr_outstanding 35.390s 16.278ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 36.520s 3.542ms 5 5 100.00
rom_ctrl_csr_rw 30.490s 13.193ms 20 20 100.00
rom_ctrl_csr_aliasing 28.250s 13.675ms 5 5 100.00
rom_ctrl_same_csr_outstanding 35.390s 16.278ms 20 20 100.00
V2 TOTAL 238 240 99.17
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 2.975m 43.237ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.162m 16.914ms 5 5 100.00
rom_ctrl_tl_intg_err 2.906m 8.182ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.162m 16.914ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.162m 16.914ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.162m 16.914ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 1.376m 16.095ms 49 50 98.00
V2S sec_cm_mem_digest rom_ctrl_smoke 1.376m 16.095ms 49 50 98.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 1.376m 16.095ms 49 50 98.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.906m 8.182ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
rom_ctrl_kmac_err_chk 1.124m 17.074ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 15.812m 91.598ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 2.975m 43.237ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.162m 16.914ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.011h 84.065ms 8 50 16.00
V3 TOTAL 8 50 16.00
TOTAL 455 500 91.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 6 6 5 83.33
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.54 96.97 93.01 97.88 100.00 98.69 97.88 98.37

Failure Buckets

Past Results