69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.578m | 8.041ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 35.110s | 3.397ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 30.720s | 4.182ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 32.530s | 14.027ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 34.270s | 4.171ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 32.520s | 9.847ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 30.720s | 4.182ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 34.270s | 4.171ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 32.900s | 7.056ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 26.670s | 33.064ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 34.920s | 18.241ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.338m | 84.249ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.172m | 34.168ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.230s | 16.047ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 34.720s | 14.406ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 34.720s | 14.406ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 35.110s | 3.397ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 30.720s | 4.182ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 34.270s | 4.171ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.780s | 7.465ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 35.110s | 3.397ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 30.720s | 4.182ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 34.270s | 4.171ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.780s | 7.465ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.034m | 90.220ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.137m | 15.477ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.941m | 4.504ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.137m | 15.477ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.137m | 15.477ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.137m | 15.477ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.578m | 8.041ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.578m | 8.041ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.578m | 8.041ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.941m | 4.504ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| rom_ctrl_kmac_err_chk | 1.172m | 34.168ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 22.454m | 138.059ms | 47 | 50 | 94.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.034m | 90.220ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.137m | 15.477ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 91 | 95 | 95.79 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.681h | 91.982ms | 8 | 50 | 16.00 |
| V3 | TOTAL | 8 | 50 | 16.00 | |||
| TOTAL | 453 | 500 | 90.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.63 | 96.97 | 93.15 | 97.88 | 100.00 | 98.69 | 97.88 | 98.83 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
0.rom_ctrl_stress_all_with_rand_reset.93069299410707388381612494876729519163790312527192950264194126760760403713323
Line 381, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10937898943 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10937898943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rom_ctrl_stress_all_with_rand_reset.66613897538977654438034614116325585314036942195203617530710267530512231844619
Line 367, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7214624913 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7214624913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
19.rom_ctrl_stress_all_with_rand_reset.56094462767872736165353087686948974617631362916949925422735570786296236574145
Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 28512370211 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x6f4d7e90
UVM_INFO @ 28512370211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rom_ctrl_stress_all_with_rand_reset.33918752831399545381607804262462539007232997626298426630774016521513942506292
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10393589068 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x17714e04
UVM_INFO @ 10393589068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
1.rom_ctrl_stress_all_with_rand_reset.27437532695613860459933112580732719211078090982538094667836947854894045395496
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:355d9077-20fb-44e8-ae72-de0dd814e308
8.rom_ctrl_stress_all_with_rand_reset.72842121616625589007275645911215502637701160358341388089121888226985760259163
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:74af55cf-ca3f-4552-b605-1c0d8361c6c8
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
1.rom_ctrl_corrupt_sig_fatal_chk.81294027494616460317650366700549932166162669275252150722190198393717270371296
Line 289, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.rom_ctrl_corrupt_sig_fatal_chk.80191361229821530326725457750725893757433061808177301227414447584595784886519
Line 279, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
13.rom_ctrl_passthru_mem_tl_intg_err.65523168328619000982869258658902370899375373637834316023369994849051443098480
Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
12.rom_ctrl_corrupt_sig_fatal_chk.89170159569022149359557167448060727599816524505115720753677210368385160655766
Line 308, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 73949440978 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 73949440978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
19.rom_ctrl_smoke.56274268681293482175077999859124711334898096559359681986843546902943078479630
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40016328640 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3d866fd1
UVM_INFO @ 40016328640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---