ROM_CTRL/64KB Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.287m	53.770ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	36.040s	17.366ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.990s	29.790ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.960s	20.819ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.890s	17.066ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.140s	35.955ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.990s	29.790ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.890s	17.066ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.420s	7.238ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	24.430s	2.716ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.370s	4.196ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	5.107m	32.204ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.174m	54.516ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	32.690s	26.574ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.240s	19.898ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.240s	19.898ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	36.040s	17.366ms	5	5	100.00
		rom_ctrl_csr_rw	32.990s	29.790ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.890s	17.066ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.330s	14.903ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	36.040s	17.366ms	5	5	100.00
		rom_ctrl_csr_rw	32.990s	29.790ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.890s	17.066ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.330s	14.903ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.806m	78.098ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.196m	4.202ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.846m	9.095ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.196m	4.202ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.196m	4.202ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.196m	4.202ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.287m	53.770ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.287m	53.770ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.287m	53.770ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.846m	9.095ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.174m	54.516ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.853m	217.681ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.806m	78.098ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.196m	4.202ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.709h	29.553ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	96.97	93.01	97.88	100.00	98.37	97.88	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.15059566311034212841192734595442904432971655826916691964394706059405850395076
    Line 348, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36540153782 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36540153782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.72410603283131943257929820788276956339854790726281533843171049143390295223545
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 799341246 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 799341246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.27219836264447001972347350361866736780910036024328382525209202027424080128054
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10797296513 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x74656870
  UVM_INFO @ 10797296513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.45625610118677544000438388202162129700203025985225458282951889853352017411213
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006541763 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb67c920f
  UVM_INFO @ 10006541763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.94771100874009644096096108028770350517325383071241292170076878064786589734591
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ac236347-3066-4849-b64f-1873353a67e2
```
  - 10.rom_ctrl_stress_all_with_rand_reset.68377284793836144781285394129201646376663825002148984133734856064980872348187
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:22d38795-819e-42a3-aea1-f657711079e4
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 5.rom_ctrl_smoke.37613680125378466291903078637029547107433675522332363821562146331498959053320
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40011800400 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf718692d
  UVM_INFO @ 40011800400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `00fe426038`