ROM_CTRL/64KB Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.299m	7.191ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.510s	20.061ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.770s	4.280ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	22.540s	8.810ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.830s	4.434ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.190s	13.443ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.770s	4.280ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.830s	4.434ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.890s	4.356ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.530s	37.076ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.720s	17.804ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.008m	95.068ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.172m	34.305ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	35.050s	20.428ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.650s	4.272ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.650s	4.272ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.510s	20.061ms	5	5	100.00
		rom_ctrl_csr_rw	31.770s	4.280ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.830s	4.434ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.310s	61.423ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.510s	20.061ms	5	5	100.00
		rom_ctrl_csr_rw	31.770s	4.280ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.830s	4.434ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.310s	61.423ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.082m	21.205ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.097m	34.067ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.897m	3.905ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.097m	34.067ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.097m	34.067ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.097m	34.067ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.299m	7.191ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.299m	7.191ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.299m	7.191ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.897m	3.905ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.172m	34.305ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.487m	104.887ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.082m	21.205ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.097m	34.067ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.616h	60.062ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	96.97	93.44	97.88	100.00	98.69	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 32 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.43925249528184374428660083342160071984414070990661106445829261527532264397442
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 534736406 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 534736406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.103840787299413450926587677837159824913958197387532800083038130489127391387947
    Line 315, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10596502423 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10596502423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.5122267511052899039481653342785637957906387028491724392892223901622887212716
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:25688b63-ddad-442b-a581-41f2d456b30a
```
  - 32.rom_ctrl_stress_all_with_rand_reset.27584488561418018254520646745351656565394665252477790692831442654353713817733
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1a90c44f-4f3e-4d51-a9d5-42e4486489f1
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.52547666538809731915809234194679745416315579175361887213243465603606609697864
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10522767030 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3bafd6f4
  UVM_INFO @ 10522767030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rom_ctrl_stress_all_with_rand_reset.67461979916468388644064274124072754162862394108867553256369165063279508033045
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10543284525 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x664748c6
  UVM_INFO @ 10543284525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 2.rom_ctrl_smoke.23759163328107349781587939709820774598406707783146544595359297025864973968167
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40022620099 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbc633e46
  UVM_INFO @ 40022620099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_smoke.100914701781722860311574927201053267024987831090247716644539344691227987434216
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40012539875 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x5ec53898
  UVM_INFO @ 40012539875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 6.rom_ctrl_kmac_err_chk.107715697216871367892450786503160998699099865293241616354154516847215630070692
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6587548340 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6587548340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `349bab6601`