ROM_CTRL/64KB Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.294m	28.140ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	34.050s	7.475ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.800s	24.371ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.780s	3.112ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	30.920s	16.752ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.980s	4.446ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.800s	24.371ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.920s	16.752ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.940s	6.150ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	29.110s	3.655ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.620s	4.459ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.875m	100.689ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.170m	17.440ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.810s	16.962ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.030s	14.788ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.030s	14.788ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	34.050s	7.475ms	5	5	100.00
		rom_ctrl_csr_rw	31.800s	24.371ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.920s	16.752ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.420s	16.077ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	34.050s	7.475ms	5	5	100.00
		rom_ctrl_csr_rw	31.800s	24.371ms	20	20	100.00
		rom_ctrl_csr_aliasing	30.920s	16.752ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.420s	16.077ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.455m	51.394ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.954m	1.625ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.931m	48.305ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.954m	1.625ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.954m	1.625ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.954m	1.625ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.294m	28.140ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.294m	28.140ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.294m	28.140ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.931m	48.305ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.170m	17.440ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	14.838m	195.760ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.455m	51.394ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.954m	1.625ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.646h	104.542ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.52	96.97	93.01	97.88	100.00	98.37	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 32 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.94173149228992686975836291579367624798680597738042970182556291077779617063439
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 821327757 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 821327757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.74366381395318279010651660711955281477703715425998109646082260534793577113736
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8791505283 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8791505283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 15.rom_ctrl_stress_all_with_rand_reset.30583433650712630080648022066316695434161243525754032710496211445759018433391
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004562100 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x28490cc2
  UVM_INFO @ 10004562100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.rom_ctrl_stress_all_with_rand_reset.99182314456062673583337608858851294344055057813917074044315971350767027839506
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10010382696 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbc1b9f57
  UVM_INFO @ 10010382696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 29.rom_ctrl_smoke.31439750953925218490852722216496506798065678521540192440098502806270440795566
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40012453261 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x66d0039
  UVM_INFO @ 40012453261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 36.rom_ctrl_stress_all.33605764130300192577803398860539962931837040522899384216417130795974888732907
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40016595266 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa391ca56
  UVM_INFO @ 40016595266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.rom_ctrl_stress_all_with_rand_reset.109305742927923691439687757699373640492285116542979734955045427664041587844633
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a4328e9f-7c3e-432a-94ea-d83903f26943
```

ROM_CTRL/64KB Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb776817a5`