ROM_CTRL/64KB Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.262m	18.748ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	38.030s	7.490ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.780s	4.278ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.370s	4.300ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	23.400s	2.369ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.320s	4.215ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.780s	4.278ms	20	20	100.00
		rom_ctrl_csr_aliasing	23.400s	2.369ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	33.100s	16.705ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	18.550s	3.046ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	36.000s	7.326ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.408m	20.524ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.149m	8.668ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.680s	41.014ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	34.960s	3.931ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	34.960s	3.931ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	38.030s	7.490ms	5	5	100.00
		rom_ctrl_csr_rw	31.780s	4.278ms	20	20	100.00
		rom_ctrl_csr_aliasing	23.400s	2.369ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	30.390s	8.571ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	38.030s	7.490ms	5	5	100.00
		rom_ctrl_csr_rw	31.780s	4.278ms	20	20	100.00
		rom_ctrl_csr_aliasing	23.400s	2.369ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	30.390s	8.571ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.431m	86.544ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.964m	8.735ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.944m	56.561ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.964m	8.735ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.964m	8.735ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.964m	8.735ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.262m	18.748ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.262m	18.748ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.262m	18.748ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.944m	56.561ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.149m	8.668ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	21.417m	509.713ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.431m	86.544ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.964m	8.735ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.076h	60.357ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.97	93.15	97.88	100.00	98.69	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 31 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.8465698459381284519659133173411633399165045823711973036014071110568507086465
    Line 330, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8780183615 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8780183615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.80032082363901311982038949598700886650889337137741313602940033031799141785366
    Line 285, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11130101214 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11130101214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.7100717644798654476134617487343858987293035276193887646633877521418893803958
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10010133118 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb790f4be
  UVM_INFO @ 10010133118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rom_ctrl_stress_all_with_rand_reset.16268712551392657169560477632083854396580849511497470969113117450200183861708
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006887318 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x86e0c6c4
  UVM_INFO @ 10006887318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.67046139716113154439633037695171429876887094789631870063760543573507901569702
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ae9eb85b-23ea-41de-a69c-57608ab14d89
```
  - 19.rom_ctrl_stress_all_with_rand_reset.110588324832087280515647819259665853201732716317075211719682436153452244342516
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d9fa1472-487d-48ba-8a59-4de3e03146d7
```
  - ... and 3 more failures.

ROM_CTRL/64KB Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1579f6a912`