ROM_CTRL/64KB Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.284m	34.793ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	28.760s	2.954ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.940s	15.204ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.790s	13.748ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.010s	6.852ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.560s	16.410ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.940s	15.204ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.010s	6.852ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.010s	8.463ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	30.420s	3.779ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	36.890s	17.145ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.043m	25.356ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.151m	38.156ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.240s	17.296ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.340s	26.006ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.340s	26.006ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	28.760s	2.954ms	5	5	100.00
		rom_ctrl_csr_rw	32.940s	15.204ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.010s	6.852ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.540s	72.108ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	28.760s	2.954ms	5	5	100.00
		rom_ctrl_csr_rw	32.940s	15.204ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.010s	6.852ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.540s	72.108ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.280m	92.695ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.205m	33.669ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.835m	38.171ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.205m	33.669ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.205m	33.669ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.205m	33.669ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.284m	34.793ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.284m	34.793ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.284m	34.793ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.835m	38.171ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
		rom_ctrl_kmac_err_chk	1.151m	38.156ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.113m	482.801ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.280m	92.695ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.205m	33.669ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.979h	32.399ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			455	500	91.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.97	93.02	97.88	100.00	98.69	98.04	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.17238436005676823143177505198259447783490992708774111592477414993002115756997
    Line 509, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32660990484 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32660990484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.39079500044850989166409363287470452528461193117097293533855140148263078746229
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1759769914 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1759769914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.8726711313498922808935994576663533301454655957550510710014888623239424235295
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10925554323 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb732a549
  UVM_INFO @ 10925554323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.rom_ctrl_stress_all_with_rand_reset.47607045323897148131683347116172181673182745471090729301356102691681388142525
    Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10046376575 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x643057af
  UVM_INFO @ 10046376575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.29223845473260208476826734382900089565252890160916156820556736625428348142351
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a6de1f12-66ac-4e4c-9686-054e7d0a6826
```
  - 7.rom_ctrl_stress_all_with_rand_reset.101511130960137039484287371415813523964554092578323968084532505698926089161814
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a295af0a-1586-477e-a8c9-a4965bd0ad03
```
  - ... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 7.rom_ctrl_corrupt_sig_fatal_chk.44439280462605321626784107105230823649216244173865631319172836077365956379900
    Line 290, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 10.rom_ctrl_passthru_mem_tl_intg_err.87103252516734080774799081944020252125367152076130542403215168512365413287430
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 10.rom_ctrl_stress_all.52991148658174370800539895538617708887550363112706441562097350324248163325207
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40071092160 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x34e45de8
  UVM_INFO @ 40071092160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2cf28c40e5`