ROM_CTRL/64KB Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.236m	28.851ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	33.950s	3.953ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.950s	4.220ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.790s	3.518ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.420s	17.103ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.810s	16.318ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.950s	4.220ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.420s	17.103ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.350s	32.811ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.830s	4.269ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.780s	17.202ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.724m	83.840ms	47	50	94.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.138m	34.992ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.540s	4.198ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.890s	16.974ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.890s	16.974ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	33.950s	3.953ms	5	5	100.00
		rom_ctrl_csr_rw	31.950s	4.220ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.420s	17.103ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.650s	4.708ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	33.950s	3.953ms	5	5	100.00
		rom_ctrl_csr_rw	31.950s	4.220ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.420s	17.103ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.650s	4.708ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.109m	28.177ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.194m	16.420ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.955m	17.610ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.194m	16.420ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.194m	16.420ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.194m	16.420ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.236m	28.851ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.236m	28.851ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.236m	28.851ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.955m	17.610ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.138m	34.992ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	21.504m	249.230ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.109m	28.177ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.194m	16.420ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.167h	139.748ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			454	500	90.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.73119219516489367293990957349710565207059688174872754373982584119196756574028
    Line 306, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47847572640 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 47847572640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.102891548569459737179577089310709619223088643276808805499651151113582304297447
    Line 369, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37321870511 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 37321870511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.82591553354749982624970547572192574729144070384943109456055600268216204029691
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3a0b7474-a013-4c49-90c0-8ddecd955a66
```
  - 7.rom_ctrl_stress_all_with_rand_reset.32724896062302679746894322843856925808477158328527878962151027583539074313376
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8d3dde50-3e48-4830-86af-49fd729fddd0
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 30.rom_ctrl_stress_all_with_rand_reset.67583542298477465662799491090241054692440163097644613334149608417110763227469
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10009732251 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xec10f75c
  UVM_INFO @ 10009732251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.rom_ctrl_stress_all_with_rand_reset.74487994100116682642296914617880375076644502850211838498101768380727571323611
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004345171 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xaa818fa3
  UVM_INFO @ 10004345171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all has 3 failures.
  - 7.rom_ctrl_stress_all.53444907587798543889695330263061434273657420753549692687043329144540311731184
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40093185120 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x684560f4
  UVM_INFO @ 40093185120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rom_ctrl_stress_all.82306295666259751131131496427362600758554004739768493847461248232151404758189
    Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40211771805 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8bd7a02e
  UVM_INFO @ 40211771805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 7.rom_ctrl_passthru_mem_tl_intg_err.88538669477244276732010120648677250456081754607201391923757930374836480670700
    Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9ae10fb42`