ROM_CTRL/64KB Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.442m	68.228ms	47	50	94.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	23.080s	7.533ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.780s	4.264ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	34.270s	4.254ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.620s	7.023ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	30.520s	15.079ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.780s	4.264ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.620s	7.023ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	27.090s	3.474ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	28.660s	3.292ms	5	5	100.00
V1		TOTAL			112	115	97.39
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.590s	4.285ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.503m	71.905ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.149m	8.666ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	31.890s	16.363ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	32.160s	3.762ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	32.160s	3.762ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	23.080s	7.533ms	5	5	100.00
		rom_ctrl_csr_rw	31.780s	4.264ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.620s	7.023ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.260s	4.023ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	23.080s	7.533ms	5	5	100.00
		rom_ctrl_csr_rw	31.780s	4.264ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.620s	7.023ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.260s	4.023ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.224m	25.103ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.986m	7.620ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.926m	5.482ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.986m	7.620ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.986m	7.620ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.986m	7.620ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.442m	68.228ms	47	50	94.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.442m	68.228ms	47	50	94.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.442m	68.228ms	47	50	94.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.926m	5.482ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.149m	8.666ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.064m	204.824ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.224m	25.103ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.986m	7.620ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.326h	48.648ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	96.89	92.13	97.68	100.00	98.62	97.30	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 32 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.102666155027327717179996309121899168993511498581042556694585293306812182693609
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 557950430 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 557950430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.99257694754460306295398154171409063616510909993602951443478596715382111966790
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 515786063 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 515786063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.113362111074084699883707939492277467361090353215609886763306415698140024084305
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12433836025 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc3ac610f
  UVM_INFO @ 12433836025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.rom_ctrl_stress_all_with_rand_reset.68791595270627084361065709424792113603357028548419648046610914646182546787790
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10497818872 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x62a5ffc4
  UVM_INFO @ 10497818872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 5 failures:

Test rom_ctrl_smoke has 3 failures.

10.rom_ctrl_smoke.55563426518031079050193735136803882304847819420687927127438942389194923722078
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 40016174534 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf7f4cbbd
  UVM_INFO @ 40016174534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.rom_ctrl_smoke.55219122376165606279796293487802920134332196017902113642427628410304532818541
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 40012142411 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x63bc4dd3
  UVM_INFO @ 40012142411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_ctrl_stress_all has 2 failures.

12.rom_ctrl_stress_all.73448226149828020381197498079710880311830558169267625266190799057634022983801
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 40018361597 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xfdbf1194
  UVM_INFO @ 40018361597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.rom_ctrl_stress_all.51310785424619438217523874388626152666590642992423463284434614747329908658079
Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 40145516427 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa86b783c
  UVM_INFO @ 40145516427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---