ROM_CTRL/64KB Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.483m	7.886ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	34.770s	9.468ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	34.130s	4.086ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.090s	16.638ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	28.090s	7.200ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.730s	39.077ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	34.130s	4.086ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.090s	7.200ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	21.390s	2.222ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.420s	4.372ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.170s	4.116ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.606m	31.237ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.171m	53.178ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.270s	16.960ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	33.810s	15.036ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	33.810s	15.036ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	34.770s	9.468ms	5	5	100.00
		rom_ctrl_csr_rw	34.130s	4.086ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.090s	7.200ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.560s	13.202ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	34.770s	9.468ms	5	5	100.00
		rom_ctrl_csr_rw	34.130s	4.086ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.090s	7.200ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.560s	13.202ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.374m	25.971ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.992m	14.100ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.894m	4.255ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.992m	14.100ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.992m	14.100ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.992m	14.100ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.483m	7.886ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.483m	7.886ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.483m	7.886ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.894m	4.255ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.171m	53.178ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.905m	521.525ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.374m	25.971ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.992m	14.100ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.699h	25.716ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.68	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.89226496449716482292470506834515735692459831060238644941482484914281779203322
    Line 467, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27041013702 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27041013702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.31410651115217399107618016722452575135227183966263800637753749030597379410905
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1090763315 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1090763315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.20193323018614745371892914671301523294654747168963415711336808585981308830035
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10506750152 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3fc3d21a
  UVM_INFO @ 10506750152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.102165625663723132595078222338925500302168850530259111721032321725196519558912
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10798874383 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2d360240
  UVM_INFO @ 10798874383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.23058136348298313719161922358972072961286728025208091577104163798593852932519
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bbb782f2-57b6-4f74-9652-068de781ccf4
```
  - 23.rom_ctrl_stress_all_with_rand_reset.19624246278376535437396917097653290750087026759381885332208355745750280488086
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:509df9d7-7f76-45ed-b67f-f78596c7c16c
```
  - ... and 3 more failures.

ROM_CTRL/64KB Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e6706fcc7b`