ROM_CTRL/64KB Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.402m	7.894ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	41.370s	4.494ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.510s	24.414ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	21.300s	2.112ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.680s	15.768ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.040s	8.213ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.510s	24.414ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.680s	15.768ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	32.470s	17.522ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	34.490s	4.427ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.450s	4.109ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.222m	16.045ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.172m	34.838ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	31.550s	3.695ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.130s	17.804ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.130s	17.804ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	41.370s	4.494ms	5	5	100.00
		rom_ctrl_csr_rw	31.510s	24.414ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.680s	15.768ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.660s	3.716ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	41.370s	4.494ms	5	5	100.00
		rom_ctrl_csr_rw	31.510s	24.414ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.680s	15.768ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.660s	3.716ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.249m	90.762ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.153m	18.203ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.874m	4.281ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.153m	18.203ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.153m	18.203ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.153m	18.203ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.402m	7.894ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.402m	7.894ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.402m	7.894ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.874m	4.281ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.172m	34.838ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.332m	178.697ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.249m	90.762ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.153m	18.203ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.513h	37.501ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 30 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.89092002734415838138698364339047282804889237828632183114746221892024784282659
    Line 327, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16115369206 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16115369206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.110059177057995127757633066600343386425565056734017176495193443818729478547666
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1507003626 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1507003626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.624684756735620688443593379496301753044938492006106094272997778844778842567
    Line 345, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 195989289150 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xff457264
  UVM_INFO @ 195989289150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.28511640189509212076432128022142512011203636784408667159062875186844414797992
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003272730 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbdba0062
  UVM_INFO @ 10003272730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 15.rom_ctrl_stress_all_with_rand_reset.68069235484260743353881630242229262155316200259349240145202690293015457887878
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fa0fbc91-a469-4cbc-9a11-6376355a914b
```
  - 17.rom_ctrl_stress_all_with_rand_reset.74273001068751065986284029552074850685108589308158686761479469928732392664295
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e79f3d31-c7f6-4d95-9bd8-52dac7c13483
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 2.rom_ctrl_smoke.51117495169601384646837438684006753204145091889025351552822101818354167829177
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40010806869 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1eb51eda
  UVM_INFO @ 40010806869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_smoke.75679518702373371382282849460798813899169531516917703451790868571537872884592
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017133189 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x850f4cf
  UVM_INFO @ 40017133189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`