9edf84e236| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.415m | 8.526ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 33.880s | 14.383ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 33.210s | 4.148ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 23.380s | 10.984ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 30.590s | 10.978ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 29.670s | 3.635ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 33.210s | 4.148ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 30.590s | 10.978ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 31.260s | 17.087ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 29.790s | 73.880ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 32.390s | 17.184ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.633m | 170.412ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.132m | 8.468ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 34.250s | 8.900ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 33.760s | 3.553ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 33.760s | 3.553ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 33.880s | 14.383ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.210s | 4.148ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 30.590s | 10.978ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.230s | 14.380ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 33.880s | 14.383ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.210s | 4.148ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 30.590s | 10.978ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.230s | 14.380ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 238 | 240 | 99.17 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.468m | 28.136ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.070m | 3.686ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.976m | 15.979ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.070m | 3.686ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.070m | 3.686ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.070m | 3.686ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.415m | 8.526ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.415m | 8.526ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.415m | 8.526ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.976m | 15.979ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.132m | 8.468ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 17.756m | 115.638ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.468m | 28.136ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.070m | 3.686ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.523h | 33.530ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 459 | 500 | 91.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.22 | 96.89 | 91.85 | 97.68 | 100.00 | 98.28 | 97.45 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
1.rom_ctrl_stress_all_with_rand_reset.29693719909845969193252738463862811029863872086838801588743585679110086835644
Line 550, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68717688283 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 68717688283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rom_ctrl_stress_all_with_rand_reset.56630373607501916499366877147158881360760118352640206705338202337843326691926
Line 352, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10870474477 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10870474477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
16.rom_ctrl_stress_all_with_rand_reset.91663744782305058400029665195848377097373999948780535057604633984299679509697
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:faee3f6b-49a4-4d4c-83de-5004008dd015
23.rom_ctrl_stress_all_with_rand_reset.12500827247121304433051740712530907866343567028587410990796159081262332848390
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8ac958eb-ee88-4a26-8f9b-22d7e0b9283d
... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
13.rom_ctrl_stress_all_with_rand_reset.47652645021883953968749407355800447768876148303980247488571383673791770647845
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003063247 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3b486a7
UVM_INFO @ 10003063247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rom_ctrl_stress_all_with_rand_reset.38747472725841099348112603444240609467594980041100761201117975757964121506328
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10004855012 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x727beb70
UVM_INFO @ 10004855012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
Test rom_ctrl_stress_all has 1 failures.
3.rom_ctrl_stress_all.977435663372897531728810126116060697243663945840108864119471326751167442881
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40342824310 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xfe638451
UVM_INFO @ 40342824310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_smoke has 1 failures.
28.rom_ctrl_smoke.112165273680718479823187761936003340536906509195701379524450692969226902810959
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40013724996 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x5b35aba9
UVM_INFO @ 40013724996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
8.rom_ctrl_corrupt_sig_fatal_chk.62627373341619200840136442568173684696109245428356058548036454894889512233934
Line 276, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 34564212138 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 34564212138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_kmac_err_chk has 1 failures.
13.rom_ctrl_kmac_err_chk.8533724363027657253167759047170652802929969005368581473721687496083062480280
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 5495776718 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 5495776718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---