ROM_CTRL/64KB Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.323m	8.070ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	36.090s	7.524ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.210s	6.089ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.660s	4.225ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	34.780s	13.852ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.190s	14.590ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.210s	6.089ms	20	20	100.00
		rom_ctrl_csr_aliasing	34.780s	13.852ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	27.560s	3.081ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	26.660s	6.063ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.240s	4.251ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	6.277m	39.122ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.177m	35.589ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.320s	4.229ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.370s	4.163ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.370s	4.163ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	36.090s	7.524ms	5	5	100.00
		rom_ctrl_csr_rw	33.210s	6.089ms	20	20	100.00
		rom_ctrl_csr_aliasing	34.780s	13.852ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.480s	8.022ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	36.090s	7.524ms	5	5	100.00
		rom_ctrl_csr_rw	33.210s	6.089ms	20	20	100.00
		rom_ctrl_csr_aliasing	34.780s	13.852ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.480s	8.022ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.385m	50.439ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.938m	994.458us	5	5	100.00
		rom_ctrl_tl_intg_err	2.983m	4.015ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.938m	994.458us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.938m	994.458us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.938m	994.458us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.323m	8.070ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.323m	8.070ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.323m	8.070ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.983m	4.015ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.177m	35.589ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.885m	100.603ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.385m	50.439ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.938m	994.458us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.487h	94.713ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			458	500	91.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.33	96.89	92.28	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 31 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.32665042260475729718066309353166411744358143520223454518641477879092362308791
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1218476550 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1218476550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.21482511855754853819411511619966789824515480677060271520843464214333644360076
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1345357411 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1345357411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 33.rom_ctrl_stress_all_with_rand_reset.29961026596100736761733562459776837421638748279167245954000356106220017793238
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006545546 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x8a7dfa9d
  UVM_INFO @ 10006545546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.60732425906481890964662866797278894297522704829515312202337871235460719338413
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006559870 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbe0a9a83
  UVM_INFO @ 10006559870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.485362074394022834861118021342022248617159954757900509902382619674757301134
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:21ae03af-83c7-428d-b0b7-31f4210afab5
```
  - 19.rom_ctrl_stress_all_with_rand_reset.31344208358669218124572748623662226088106587420938971276673686078049713630981
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f6ed5217-2742-4151-bc8d-f7a03ea83aa1
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 19.rom_ctrl_smoke.113047414056236496993622142242601784542486628725626361998981226243977707619396
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40018234440 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x98d121bb
  UVM_INFO @ 40018234440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.rom_ctrl_smoke.23946805743346417721092842769294965959641007414570876108085061955007334115929
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40007719334 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xafee54a9
  UVM_INFO @ 40007719334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 34.rom_ctrl_stress_all.40200416199443534573050593423901523259706266397098889843631179118578641598639
    Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40242624101 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xdb8351a3
  UVM_INFO @ 40242624101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 8.rom_ctrl_passthru_mem_tl_intg_err.46454058628721859724604344598838084446055501315129482484885174719201745979913
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`