ROM_CTRL/64KB Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.452m	33.963ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.790s	14.850ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	34.470s	66.041ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.400s	9.465ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	33.340s	29.179ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.040s	20.564ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	34.470s	66.041ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.340s	29.179ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.340s	14.547ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	28.980s	3.403ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.530s	4.347ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.064m	16.912ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.139m	7.756ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.180s	8.361ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.770s	6.728ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.770s	6.728ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.790s	14.850ms	5	5	100.00
		rom_ctrl_csr_rw	34.470s	66.041ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.340s	29.179ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.850s	15.023ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.790s	14.850ms	5	5	100.00
		rom_ctrl_csr_rw	34.470s	66.041ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.340s	29.179ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.850s	15.023ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.322m	92.629ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.075m	14.200ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.932m	8.142ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.075m	14.200ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.075m	14.200ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.075m	14.200ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.452m	33.963ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.452m	33.963ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.452m	33.963ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.932m	8.142ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.139m	7.756ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.774m	466.039ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.322m	92.629ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.075m	14.200ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.876h	112.253ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.13	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.112047112668929497896542745915925766544513415987843392843950655157207922302774
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 749667434 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 749667434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.39278865404388551652516884908345339160704594220206398020873321583549010908356
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 933526442 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 933526442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.31588266445003619423551832827924145711283537343623553887250683348704844690595
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b15742b1-895e-4cc8-9684-e8c892b7ed89
```
  - 3.rom_ctrl_stress_all_with_rand_reset.63747412653154301712497746666594156702149641362277022880780384760943763289414
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ea20ff19-7b8b-470c-99e4-48f6555d7b6a
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.48911420835062827843743644165843264950705119496677179853058196929726756259138
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10361561071 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf15de59a
  UVM_INFO @ 10361561071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.rom_ctrl_stress_all_with_rand_reset.20672689635444118003345853876854897896471686485097306727449617723542799141554
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10646034991 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2255ddd2
  UVM_INFO @ 10646034991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 9.rom_ctrl_stress_all.45133039859656205945964543153338155830339666196307025491475584150397160516210
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40017483285 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x710f2cd8
  UVM_INFO @ 40017483285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a04e34f557`