ROM_CTRL/64KB Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.257m	7.875ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.400s	5.376ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	30.600s	9.816ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.410s	3.951ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	28.110s	41.057ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	29.410s	7.433ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	30.600s	9.816ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.110s	41.057ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	28.680s	14.239ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.710s	4.433ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.170s	16.489ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.711m	26.379ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.141m	38.577ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.950s	9.829ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	35.520s	41.638ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	35.520s	41.638ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.400s	5.376ms	5	5	100.00
		rom_ctrl_csr_rw	30.600s	9.816ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.110s	41.057ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.690s	4.103ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.400s	5.376ms	5	5	100.00
		rom_ctrl_csr_rw	30.600s	9.816ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.110s	41.057ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.690s	4.103ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.396m	185.521ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.190m	4.272ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.956m	5.721ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.190m	4.272ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.190m	4.272ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.190m	4.272ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.257m	7.875ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.257m	7.875ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.257m	7.875ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.956m	5.721ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.141m	38.577ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	14.804m	85.355ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.396m	185.521ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.190m	4.272ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.642h	161.964ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			459	500	91.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.64467393919735354510395622932197648570868706667593960584335843656990635139320
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429647640 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 429647640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.80057750896341522466374519995397579333470766516089675196822405822522951283478
    Line 552, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19304016224 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19304016224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.64265898198767146140866047700709708660517939894234089082850090237293294485835
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:700c7c1f-395e-41f2-999a-3763fef39d9f
```
  - 3.rom_ctrl_stress_all_with_rand_reset.16265463318601578252056655367664392548787287106654009393053299482255134608859
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8e055247-f08d-408b-bc6d-ffb49dd9127f
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.76868937964510414924083924373905946479066747023590688118042141125328529177007
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11146490116 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x27f2f628
  UVM_INFO @ 11146490116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.66440476072661661549847405954223115945323859033336237090004761349493265932840
    Line 265, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10480396951 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa3cb8638
  UVM_INFO @ 10480396951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.rom_ctrl_stress_all_with_rand_reset.8658831237450035007411042826800702355437553180693927593975415516036416650588
    Line 469, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 423413680515 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 423413680515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39211701b5`