edf2fd5092| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.356m | 8.838ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 25.760s | 2.699ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 33.480s | 16.590ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 24.690s | 2.606ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 33.500s | 24.992ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 32.810s | 4.169ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 33.480s | 16.590ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 33.500s | 24.992ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 32.780s | 25.123ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 32.350s | 4.203ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.220s | 8.916ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.107m | 38.464ms | 48 | 50 | 96.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.141m | 35.063ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.070s | 4.270ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 36.770s | 19.965ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 36.770s | 19.965ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 25.760s | 2.699ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.480s | 16.590ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 33.500s | 24.992ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 38.000s | 29.624ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 25.760s | 2.699ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.480s | 16.590ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 33.500s | 24.992ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 38.000s | 29.624ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 238 | 240 | 99.17 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.212m | 130.322ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.865m | 3.866ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.837m | 11.576ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.865m | 3.866ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.865m | 3.866ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.865m | 3.866ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.356m | 8.838ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.356m | 8.838ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.356m | 8.838ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.837m | 11.576ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.141m | 35.063ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 16.544m | 377.252ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.212m | 130.322ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.865m | 3.866ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.673h | 59.097ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 455 | 500 | 91.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.21 | 96.89 | 91.99 | 97.68 | 100.00 | 98.28 | 97.30 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
2.rom_ctrl_stress_all_with_rand_reset.107650184536525976755955478808823550577395151895553025043380699051393453948076
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1028853716 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1028853716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rom_ctrl_stress_all_with_rand_reset.10388225157979211266254937665038182912232123563682734510065882089911207595753
Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3243952614 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3243952614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
12.rom_ctrl_stress_all_with_rand_reset.56871367380115067117618833549145788155641318650924262136808752678819797761325
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:c1d9a8af-d8d5-42c3-86dc-48cfcba79f7d
24.rom_ctrl_stress_all_with_rand_reset.41050085084586081348943116417821598912850893931987040004977025033623587397633
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:827eece9-a62b-4c5b-aec9-df28716e7825
... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
0.rom_ctrl_stress_all_with_rand_reset.88213883729693501858709552341705656612331923251903107364638385382436766579439
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10010106906 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3b66002e
UVM_INFO @ 10010106906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.5765538103651588669172878621602029550461004694719979610366555196072993901147
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10009944920 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbc6285b6
UVM_INFO @ 10009944920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
Test rom_ctrl_smoke has 1 failures.
13.rom_ctrl_smoke.104785817808994098121219435798213747476558036078170539891397098485033431454727
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40009022919 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x923f6fd4
UVM_INFO @ 40009022919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all has 2 failures.
14.rom_ctrl_stress_all.31049997610630060110574914783465777328839384877237068557222504461642661203016
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40012941668 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x82ff2a76
UVM_INFO @ 40012941668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rom_ctrl_stress_all.75041838356969349541644190305208998638170145576821745042020895600120726559938
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40011052942 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x20a65886
UVM_INFO @ 40011052942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
37.rom_ctrl_corrupt_sig_fatal_chk.10584017187844569950637690362412083390996271227847351392796792386517709727229
Line 297, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---