ROM_CTRL/64KB Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.555m	32.694ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	30.790s	11.778ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.790s	17.798ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	24.960s	2.863ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	19.650s	7.479ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.760s	8.595ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.790s	17.798ms	20	20	100.00
		rom_ctrl_csr_aliasing	19.650s	7.479ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.440s	3.458ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	33.840s	34.801ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.450s	17.740ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.524m	29.959ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.137m	16.790ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	36.390s	71.402ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.820s	73.999ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.820s	73.999ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	30.790s	11.778ms	5	5	100.00
		rom_ctrl_csr_rw	33.790s	17.798ms	20	20	100.00
		rom_ctrl_csr_aliasing	19.650s	7.479ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.420s	5.021ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	30.790s	11.778ms	5	5	100.00
		rom_ctrl_csr_rw	33.790s	17.798ms	20	20	100.00
		rom_ctrl_csr_aliasing	19.650s	7.479ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.420s	5.021ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.312m	48.286ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.824m	941.594us	5	5	100.00
		rom_ctrl_tl_intg_err	2.959m	4.128ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.824m	941.594us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.824m	941.594us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.824m	941.594us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.555m	32.694ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.555m	32.694ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.555m	32.694ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.959m	4.128ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.137m	16.790ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	14.186m	191.911ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.312m	48.286ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.824m	941.594us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.546h	49.401ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			459	500	91.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.85562358837479324752494190185676501733912918285119631523837079761142248268907
    Line 484, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 68936863596 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 68936863596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.39681737191382204809027694021681327178340204672117832204374494174517751631632
    Line 665, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49401125788 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49401125788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.72632185915037029215006818040252513970890245717596565364610741182926192367321
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6798b062-c738-4378-9285-7f36bf887530
```
  - 19.rom_ctrl_stress_all_with_rand_reset.91229565277499445577533547538369925901178441374554624787256945102276311902056
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5bbd1bc6-adba-4e00-b0fe-536b1792c685
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.3550897064097745249504974653923244772705113549817509371774753226865230190008
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005728266 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3b65f7fc
  UVM_INFO @ 10005728266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.112051433138950738341010348807689131972482566749431016322912112940883595720363
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013202636 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf84baf99
  UVM_INFO @ 10013202636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 4.rom_ctrl_passthru_mem_tl_intg_err.80768008688154908329180451431535680078750124152470314565922584003015143788058
    Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 27.rom_ctrl_kmac_err_chk.85897836271275508946799411264582810841350469556176717684833772473433404622260
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6593212497 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6593212497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`