ROM_CTRL/64KB Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.390m	17.082ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	36.340s	8.745ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.040s	16.120ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.050s	3.674ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	25.670s	15.007ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.690s	8.377ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.040s	16.120ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.670s	15.007ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.370s	31.024ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.830s	15.949ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.350s	24.933ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.043m	65.718ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.152m	8.887ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.150s	41.864ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	35.710s	4.284ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	35.710s	4.284ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	36.340s	8.745ms	5	5	100.00
		rom_ctrl_csr_rw	33.040s	16.120ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.670s	15.007ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.970s	3.504ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	36.340s	8.745ms	5	5	100.00
		rom_ctrl_csr_rw	33.040s	16.120ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.670s	15.007ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.970s	3.504ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.406m	35.468ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.102m	21.989ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.922m	18.461ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.102m	21.989ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.102m	21.989ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.102m	21.989ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.390m	17.082ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.390m	17.082ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.390m	17.082ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.922m	18.461ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.152m	8.887ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.230m	96.596ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.406m	35.468ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.102m	21.989ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.703h	100.535ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 36 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.112811916158135801623485078739974747402484373022593487419400440753411922966085
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 201191460 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 201191460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.70152092256600410100471261006763633278944518038651269508789450613710457211427
    Line 319, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11987569157 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11987569157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.114897199300842116192863835037968817980931021833526858596184674488780690745140
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4d1deac7-7ae2-4a99-95bd-f0699ac2d8c5
```
  - 18.rom_ctrl_stress_all_with_rand_reset.22918660460043953496414116870199409522322315076905187955821505680157828113137
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:697efb45-772a-4fdc-a012-a2e80968148e
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 28.rom_ctrl_stress_all.60703824034278671098986313219887751499791963760934541964356964558907517828701
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40015851479 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x82b4e917
  UVM_INFO @ 40015851479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.rom_ctrl_stress_all_with_rand_reset.2998074388394421348441472442746124938075778126418875171438423141072965420745
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004908854 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa01c5ecd
  UVM_INFO @ 10004908854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5967df933a`