ROM_CTRL/64KB Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.326m	22.974ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.560s	2.895ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.460s	17.056ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.250s	19.566ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.140s	6.495ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.150s	4.247ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.460s	17.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.140s	6.495ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	31.390s	14.612ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.110s	5.078ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.240s	12.769ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.347m	86.567ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.119m	8.177ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	35.190s	4.469ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.610s	53.269ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.610s	53.269ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.560s	2.895ms	5	5	100.00
		rom_ctrl_csr_rw	32.460s	17.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.140s	6.495ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.550s	4.268ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.560s	2.895ms	5	5	100.00
		rom_ctrl_csr_rw	32.460s	17.056ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.140s	6.495ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.550s	4.268ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.372m	51.409ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.055m	2.813ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.038m	18.739ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.055m	2.813ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.055m	2.813ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.055m	2.813ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.326m	22.974ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.326m	22.974ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.326m	22.974ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.038m	18.739ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.119m	8.177ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	17.331m	103.554ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.372m	51.409ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.055m	2.813ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.605h	65.049ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			454	500	90.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.13	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.88596844372358179030599870273586915029234196105597285775312830260354933835202
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1378821101 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1378821101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.71438342674197905781232805001056162638596758072980053975058569082146357251012
    Line 790, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 235729497863 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 235729497863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.588681844245684219493728623391983421455585217583173683075405326151788312687
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:88f996b8-7ce4-4f6c-be1f-bbfd6c04dbe2
```
  - 17.rom_ctrl_stress_all_with_rand_reset.95520315276834485899605656503170925263709176928913475840268976886022974897201
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2ad0f877-1341-4615-8cd9-270a0dde70b4
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.27030127744699400699142061149987327273361766669690932727143069769007912787580
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005687898 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x11ca4604
  UVM_INFO @ 10005687898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.rom_ctrl_stress_all_with_rand_reset.99225818693618609772591080271778461249574445252347374147373049388626338116802
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005986083 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x32b1ce5e
  UVM_INFO @ 10005986083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 38.rom_ctrl_smoke.14335697714177213884872538271368733111010136611385007885852954500570713191114
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40010440959 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa7ee894
  UVM_INFO @ 40010440959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.rom_ctrl_smoke.19536393307018017018668190951742325830542028818807368249820564817726891261313
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017412336 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe80e0666
  UVM_INFO @ 40017412336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 6.rom_ctrl_passthru_mem_tl_intg_err.84906303400495294700278862664283543391668919151621061857039735377987364085727
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d51405297e`