ROM_CTRL/64KB Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.309m	18.310ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	30.290s	35.186ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.090s	18.473ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.200s	5.279ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.640s	66.284ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.680s	8.550ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.090s	18.473ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.640s	66.284ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	26.750s	11.721ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	29.790s	7.217ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.190s	4.149ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.079m	94.808ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.165m	161.363ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	30.260s	7.546ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.510s	4.192ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.510s	4.192ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	30.290s	35.186ms	5	5	100.00
		rom_ctrl_csr_rw	33.090s	18.473ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.640s	66.284ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	29.050s	15.682ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	30.290s	35.186ms	5	5	100.00
		rom_ctrl_csr_rw	33.090s	18.473ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.640s	66.284ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	29.050s	15.682ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.440m	102.378ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.906m	8.619ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.928m	4.346ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.906m	8.619ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.906m	8.619ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.906m	8.619ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.309m	18.310ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.309m	18.310ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.309m	18.310ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.928m	4.346ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
		rom_ctrl_kmac_err_chk	1.165m	161.363ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	22.279m	127.335ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.440m	102.378ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.906m	8.619ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.746h	86.049ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.6754028125464129991451620316450909778335865057847271828176197961165329181295
    Line 285, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5061832141 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5061832141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.70044960905188243444316554272815214918314542307585106854986426649785893326805
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2261616183 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2261616183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.64289739721942235914615034677501192247357094669047116715939568637705449353369
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:be5f5c9b-5de8-40d9-98aa-61893626e9e9
```
  - 12.rom_ctrl_stress_all_with_rand_reset.83037510606854787339540958746814903024087980034475049042561683749610711774844
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:dd0bed0c-2100-479d-83c4-969a06946175
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.14474707094743866088941100264125041718441170720335007576158745436328341776281
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10011236053 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xab4f637c
  UVM_INFO @ 10011236053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.83673497735781075267165826034434918757655559073000325990585692530601409037313
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10131885739 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x8f7ffe2b
  UVM_INFO @ 10131885739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 5.rom_ctrl_corrupt_sig_fatal_chk.56206587803163302174351515386776204402023048783215193620924268816888401743815
    Line 297, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 7.rom_ctrl_passthru_mem_tl_intg_err.11133495992249377544058672461462097799990958636490099565011916394231489208577
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 10.rom_ctrl_smoke.88208854343942838176569103411555890150689142728656496321177822927361231343082
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40015027061 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x360e99be
  UVM_INFO @ 40015027061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_smoke.32406018816348306575109606517356016567726753095837967308100827021164755996347
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40009815677 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6ce915bc
  UVM_INFO @ 40009815677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `974aaab627`