ROM_CTRL/64KB Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.359m	60.608ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	30.490s	12.104ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	30.150s	15.113ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.570s	25.081ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.330s	8.040ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.040s	14.155ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	30.150s	15.113ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.330s	8.040ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.110s	3.627ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	29.710s	13.303ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.230s	4.226ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.288m	78.876ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.162m	8.043ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.350s	4.243ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.590s	4.316ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.590s	4.316ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	30.490s	12.104ms	5	5	100.00
		rom_ctrl_csr_rw	30.150s	15.113ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.330s	8.040ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.970s	29.281ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	30.490s	12.104ms	5	5	100.00
		rom_ctrl_csr_rw	30.150s	15.113ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.330s	8.040ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	34.970s	29.281ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.177m	96.352ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.147m	4.130ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.877m	4.198ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.147m	4.130ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.147m	4.130ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.147m	4.130ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.359m	60.608ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.359m	60.608ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.359m	60.608ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.877m	4.198ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.162m	8.043ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.084m	289.552ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.177m	96.352ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.147m	4.130ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.638h	56.178ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	96.89	91.99	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.87108097487848316161005103462592796003356678612495083966790410209850353774113
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 772230799 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 772230799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.23449482007420396513734886040904252042930320205528674483887687618031240903026
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3383450218 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3383450218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.111807146252074586151967469905111809569230627971660556228530011909454738249099
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10703594440 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa4a47816
  UVM_INFO @ 10703594440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.45549757323878589933933503335227974773138284572474147752034071428868975487373
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11005368779 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x10d731e1
  UVM_INFO @ 11005368779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.38176168324141397482889054686249762935280183454682639668681086187950098817080
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:278de7df-763b-4cd3-a152-73aff772fbc4
```
  - 21.rom_ctrl_stress_all_with_rand_reset.83194591272276147389845277695561528105451305169272884779813137978373018327001
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a4700731-295f-4d95-91f3-8b2aa7c09d0c
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 37.rom_ctrl_smoke.102462459780044483139472226133852517192836620762575709857434701826815909584230
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40010960471 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8012ee5b
  UVM_INFO @ 40010960471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.rom_ctrl_smoke.55261770661927339851111414780461231335563077031978222816059460258917719373130
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40012106740 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x68d671f0
  UVM_INFO @ 40012106740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 17.rom_ctrl_passthru_mem_tl_intg_err.108009760713802062418346328533210034168243078983727881572476403633159747137902
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`