ROM_CTRL/64KB Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.432m	8.530ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	22.720s	1.133ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.810s	4.357ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.710s	29.597ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.570s	13.650ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.810s	17.256ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.810s	4.357ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.570s	13.650ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.820s	3.871ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	29.590s	14.463ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.620s	4.170ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.190m	25.103ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.101m	19.908ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.500s	34.819ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	31.690s	12.763ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	31.690s	12.763ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	22.720s	1.133ms	5	5	100.00
		rom_ctrl_csr_rw	31.810s	4.357ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.570s	13.650ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.490s	8.346ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	22.720s	1.133ms	5	5	100.00
		rom_ctrl_csr_rw	31.810s	4.357ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.570s	13.650ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.490s	8.346ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.320m	25.667ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.136m	16.891ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.933m	4.215ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.136m	16.891ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.136m	16.891ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.136m	16.891ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.432m	8.530ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.432m	8.530ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.432m	8.530ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.933m	4.215ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.101m	19.908ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.430m	323.686ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.320m	25.667ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.136m	16.891ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.512h	41.536ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.39	96.89	91.99	97.68	100.00	98.62	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 32 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.95719028764636969187073919464164735235783945852272382027984737205612385769599
    Line 410, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16332420305 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16332420305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.26189665992495121785603205772102989100089204482569087058555883157047941927616
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1396726861 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1396726861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.56833614552524661210496806819843203212564029793948157455375738311060861065093
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004781119 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xff1c1ef6
  UVM_INFO @ 10004781119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.58531901038663788899148822827428084865475010427026159662242686345679563019167
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10619616351 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3d2f8913
  UVM_INFO @ 10619616351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.7540998670837031207443655226840962295110518254770678883780269401381800380399
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:da3222bf-8f44-437a-a71a-284e2e22c1d4
```
  - 3.rom_ctrl_stress_all_with_rand_reset.85265354797163760593975415667795773812783871002899006994693664153935355935963
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:aeeed15a-ff0d-4d30-8519-c2fe59a1fbbd
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.69345661461969538006598049481563671785308806923790153211071125873448357340506
    Line 1001, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 896227075123 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 896227075123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 33.rom_ctrl_smoke.56140319008152770549552157838841528492283078220917302083419543623935879855407
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017164211 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xff7f04bd
  UVM_INFO @ 40017164211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`