ROM_CTRL/64KB Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.355m	8.056ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.300s	15.355ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.690s	19.581ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.700s	15.379ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.210s	16.635ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.170s	3.902ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.690s	19.581ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.210s	16.635ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	34.480s	4.354ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	35.360s	16.388ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	36.280s	7.908ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.671m	32.771ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.139m	16.734ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	35.370s	26.265ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.670s	16.318ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.670s	16.318ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.300s	15.355ms	5	5	100.00
		rom_ctrl_csr_rw	32.690s	19.581ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.210s	16.635ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.280s	16.126ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.300s	15.355ms	5	5	100.00
		rom_ctrl_csr_rw	32.690s	19.581ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.210s	16.635ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.280s	16.126ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.159m	24.674ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.938m	5.364ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.861m	18.273ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.938m	5.364ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.938m	5.364ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.938m	5.364ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.355m	8.056ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.355m	8.056ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.355m	8.056ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.861m	18.273ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.139m	16.734ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.313m	405.554ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.159m	24.674ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.938m	5.364ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.052h	27.330ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.68	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 33 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.92998644451813977549782720830359403833374287293952568502429915209787679865948
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 974261108 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 974261108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.57266396817606587668813047932939861559385376307142976641510263171021328789085
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 295205063 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 295205063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.64001290695202110698106610877138407806384368922132625363436566055358004535222
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11648178389 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x76a2fc82
  UVM_INFO @ 11648178389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.30347576488207967606292197292039513699522517165811082575249924464677936362355
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004302600 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xea04055a
  UVM_INFO @ 10004302600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.44434492961620654902526942905632502251165219653457388569654013975147267750635
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9873790a-6ce1-4a61-af91-ee4982a4524d
```
  - 17.rom_ctrl_stress_all_with_rand_reset.46770733963091508158236509721161201382321891973294732936714775713068128273425
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:04fbeae3-6d62-46ab-9fb8-b0bf7e1a5ffb
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 11.rom_ctrl_passthru_mem_tl_intg_err.107243860914513893316744523541239652364826461436728603152808350732400697836153
    Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 16.rom_ctrl_smoke.9149332611245066481839816106630771667341004685696241714454719724365533401461
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40009211461 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x9fe40bf9
  UVM_INFO @ 40009211461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`