ROM_CTRL/64KB Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.220m	8.394ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.420s	12.095ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	27.710s	3.382ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	31.800s	7.737ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	26.970s	3.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.240s	17.258ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	27.710s	3.382ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.970s	3.147ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.410s	8.522ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.950s	8.395ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.050s	8.775ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.321m	20.517ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.143m	8.456ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.180s	4.153ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.500s	4.259ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.500s	4.259ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.420s	12.095ms	5	5	100.00
		rom_ctrl_csr_rw	27.710s	3.382ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.970s	3.147ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.290s	15.529ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.420s	12.095ms	5	5	100.00
		rom_ctrl_csr_rw	27.710s	3.382ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.970s	3.147ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.290s	15.529ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.235m	42.557ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.995m	11.483ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.857m	4.023ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.995m	11.483ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.995m	11.483ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.995m	11.483ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.220m	8.394ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.220m	8.394ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.220m	8.394ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.857m	4.023ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.143m	8.456ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.788m	188.824ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.235m	42.557ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.995m	11.483ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.820h	111.906ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			459	500	91.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.28989318365105253680445293082809731136111366678154441450133508925821143928913
    Line 340, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 88926055486 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 88926055486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.49923299306842412836260774847606890699062890951521435989069655262846554577187
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 396071038 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 396071038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.36448771035011051716199681908286605875735350301194011659533938693238213646984
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7b25676d-d8b2-4d7d-8556-9c3a25e242d8
```
  - 16.rom_ctrl_stress_all_with_rand_reset.56521547370275010645243753610902889507045406773312041437064914360279819167789
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0109d6d9-ca2c-4785-91b5-bdaf68cd9eb2
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.11131059075039479640472962323322486689610436198297847714237892449455597259623
    Line 366, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 140111062834 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 140111062834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rom_ctrl_stress_all_with_rand_reset.78099488378214560599584705309686593966212200683431082554902103351367304100414
    Line 1242, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2242502044653 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2242502044653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 2 failures.
  - 13.rom_ctrl_smoke.34456423067160604059452194780204981747334250719411679765734820262621238542402
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40020534221 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf1caaf69
  UVM_INFO @ 40020534221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_smoke.94276813034502187343347701936146889748652102091496832886147020446522070883704
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40016449775 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xaee6403c
  UVM_INFO @ 40016449775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 20.rom_ctrl_stress_all_with_rand_reset.64754164090263028604546420617308467991724725393507493798542486841989651880188
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004775727 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcc4c52
  UVM_INFO @ 10004775727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.rom_ctrl_stress_all_with_rand_reset.60768244926880851321919790717302451040841014916192926827247251026269432833992
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006901096 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xba7608fc
  UVM_INFO @ 10006901096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e0219a2c5`