ROM_CTRL/64KB Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.525m	8.470ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	32.710s	3.065ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.090s	32.245ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.960s	1.442ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.290s	4.121ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.340s	16.542ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.090s	32.245ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.290s	4.121ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	28.180s	4.507ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	32.450s	5.262ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.240s	9.437ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.499m	90.462ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.244m	71.331ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.670s	4.234ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.430s	15.307ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.430s	15.307ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	32.710s	3.065ms	5	5	100.00
		rom_ctrl_csr_rw	31.090s	32.245ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.290s	4.121ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.480s	17.228ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	32.710s	3.065ms	5	5	100.00
		rom_ctrl_csr_rw	31.090s	32.245ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.290s	4.121ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.480s	17.228ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.336m	26.693ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.046m	13.874ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.885m	18.281ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.046m	13.874ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.046m	13.874ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.046m	13.874ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.525m	8.470ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.525m	8.470ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.525m	8.470ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.885m	18.281ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.244m	71.331ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	12.945m	312.042ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.336m	26.693ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.046m	13.874ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.273h	35.240ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.13	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 35 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.8560265646528727361682237647986039512825097996579788350084860035789657839747
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 545092989 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 545092989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.91396450023383137042630953765152526052751876267196205084956875158971695732093
    Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1335713325 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1335713325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.96528672267242277007249501404587376233601604101805346775991374314295293067756
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10819415905 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcc9f9239
  UVM_INFO @ 10819415905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rom_ctrl_stress_all_with_rand_reset.20946715949904915481427315958644541377673847179276568626264080987390044742130
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004798725 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2f1bc958
  UVM_INFO @ 10004798725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 21.rom_ctrl_stress_all_with_rand_reset.13752341825123119688105748786219654182461303524438633812566142761889543797205
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9dff1651-0a3a-4d1f-8cda-8eed8bd1b05a
```
  - 46.rom_ctrl_stress_all_with_rand_reset.20002180249238965070412097406755928689588108681976240978404900421406812517819
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9795f928-6720-4ed8-a73d-4426f2e8b6b4
```

ROM_CTRL/64KB Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0bfa990ddc`